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Method of improving error checking and correction performance of memory

  • US 9,779,838 B2
  • Filed: 08/28/2015
  • Issued: 10/03/2017
  • Est. Priority Date: 08/28/2014
  • Status: Active Grant
First Claim
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1. A method of improving an error checking and correction performance of a memory, the method comprising:

  • replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells;

    storing check bits of error correction code in a non-defective memory cell of the defective column, and further storing check bits of error correction code in a memory cell of another spare column of the spare cell array only if another spare column is available;

    storing defect information regarding the defective memory cell in an information storing spare column of the spare cell array;

    deciding whether a memory cell of the defective column is to be used to perform error checking and correction on a memory, based on the defect information stored in the information storing spare column; and

    performing error checking and correction using the memory cell decided based on a result of the deciding step.

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