Method of improving error checking and correction performance of memory
First Claim
1. A method of improving an error checking and correction performance of a memory, the method comprising:
- replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells;
storing check bits of error correction code in a non-defective memory cell of the defective column, and further storing check bits of error correction code in a memory cell of another spare column of the spare cell array only if another spare column is available;
storing defect information regarding the defective memory cell in an information storing spare column of the spare cell array;
deciding whether a memory cell of the defective column is to be used to perform error checking and correction on a memory, based on the defect information stored in the information storing spare column; and
performing error checking and correction using the memory cell decided based on a result of the deciding step.
1 Assignment
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Accused Products
Abstract
A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.
10 Citations
16 Claims
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1. A method of improving an error checking and correction performance of a memory, the method comprising:
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replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in a non-defective memory cell of the defective column, and further storing check bits of error correction code in a memory cell of another spare column of the spare cell array only if another spare column is available; storing defect information regarding the defective memory cell in an information storing spare column of the spare cell array; deciding whether a memory cell of the defective column is to be used to perform error checking and correction on a memory, based on the defect information stored in the information storing spare column; and performing error checking and correction using the memory cell decided based on a result of the deciding step. - View Dependent Claims (2, 3, 4, 5)
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6. A method of improving an error checking and correction performance of a memory, the method comprising:
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replacing a defective column including a defective memory cell of a memory cell array with a spare column of a spare cell array, wherein the memory cell array comprises memory cells in a matrix, and the spare cell array comprises spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding the defective memory cell in a storage unit; selecting whether the at least one non-defective memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of selecting whether the at least one non-defective memory cell storing the check bits is to be used. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of improving error checking and correction in a memory, the method comprising:
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replacing, in a memory cell array of memory cells in a matrix, a column containing a defective memory cell (DMC) with a spare column—
free of any DMCs—
of a spare cell array (SCA) of spare memory cells in a matrix;storing check bits of error correction code in a memory cell of any spare column that remains in the SCA after the replacing, only if any spare column remains in the SCA after the replacing; storing check bits of error correction code in a non-defective memory cell of a column containing any DMC that has replaced any spare column of the SCA; storing defect information regarding a location of the DMC within the replaced defective column in an information storing spare column (ISSC) of the SCA, wherein the ISSC is designated to remain in the SCA; selecting, based on the defect information, whether to use at least one memory cell for performing error checking and correction in the memory; and performing error checking and correction in the memory based on the selecting. - View Dependent Claims (16)
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Specification