Method of fabricating 3D NAND

• US 9,779,948 B1
• Filed: 06/17/2016
• Issued: 10/03/2017
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Baraskar, Ashish, Zhang, Yanli, Lu, Ching-Huang, Lu, Zhenyu
• Primary Examiner(s): Henry, Caleb
• Assistant Examiner(s): Amer, Mounir
• Application Number:
  US15/185,866
• Time in Patent Office: 473 Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.

Claims

1. A method of fabricating non-volatile storage, the method comprising:

forming a stack of alternating layers of a first material and a second material over a substrate, the first material having an etch selectively with respect to the second material;

creating a first opening through the stack of alternating layers;

forming a semiconductor in the first opening;

creating a second opening in the stack of alternating layers of the first material and the second material;

removing a layer of the second material to form a recess that exposes a sidewall of the semiconductor;

introducing a dopant into the recess by way of the second opening to dope the semiconductor; and

forming a control gate in the recess for a transistor, the doped semiconductor serving as a body for the transistor.

2. The method of claim 1, wherein the forming the semiconductor in the first opening comprises:

forming crystalline silicon in the first opening.

3. The method of claim 1, wherein the forming the semiconductor in the first opening comprises:

epitaxially growing crystalline silicon in the first opening upwards from the substrate.

4. The method of claim 1, wherein the introducing the dopant into the second opening and into the recess to dope the semiconductor comprises:

performing gas phase doping.

5. The method of claim 1, wherein the introducing the dopant into the second opening and into the recess to dope the semiconductor comprises:

performing boron gas phase doping.

6. The method of claim 1, wherein the introducing the dopant into the second opening and into the recess to dope the semiconductor comprises:

performing monolayer doping.

7. The method of claim 1, wherein the introducing the dopant into the second opening and into the recess to dope the semiconductor comprises:

performing plasma doping.

8. The method of claim 1, further comprising:

forming a memory cell film for memory cells of a NAND string in the first opening, the transistor being a select transistor of the NAND string.

9. The method of claim 8, further comprising:

forming a conductive layer in the second opening down to the substrate, the conductive layer serving as a source line for the NAND string, wherein the select transistor couples the NAND string to the source line.

10. The method of claim 9, wherein the dopant has a first type of conductivity, further comprising:

doping a portion of the substrate below the second opening with a dopant having a second type of conductivity, wherein the portion of the substrate below the second opening is exposed when introducing the dopant having the first type of conductivity into the second opening, wherein after doping the portion of the substrate below the second opening with the dopant having the second type of conductivity and after introducing the dopant having the first type of conductivity into the second opening the portion of the substrate below the second opening has a net doping of the second type of conductivity.

11. The method of claim 8, further comprising:

forming a first conductive layer on substrate, wherein the select transistor couples the NAND string to the first conductive layer on substrate; and

forming a second conductive layer in the second opening down to the first conductive layer, the first and second conductive layers serving as a source line for the NAND string.

12. A method of fabricating three-dimensional NAND, the method comprising:

forming a stack of alternating horizontal layers of a first material and a second material over a substrate, the first material having an etch selectively with respect to the second material;

etching a vertical memory hole through the stack of alternating horizontal layers, the vertical memory hole having a vertical sidewall;

forming silicon for a body of a source side select transistor for a NAND string in the vertical memory hole, the silicon covers the vertical sidewall of the memory hole near the substrate;

forming a memory cell film on the vertical sidewall of the memory hole above the silicon for the body, the memory cell film for memory cells of the NAND string;

etching a vertical opening in the stack of alternating horizontal layers;

etching away the horizontal layers of the second material to form horizontal recesses in the stack, a first of the horizontal recesses exposes the silicon for the body of the source side select transistor;

introducing a dopant into the first horizontal recess by way of the vertical opening to dope the body of the source side select transistor; and

forming a conductive material in the horizontal recesses, the conductive material serving as control gates of the memory cells of the NAND string and as a control gate of the source side select transistor of the NAND string.

13. The method of claim 12, wherein the forming silicon for the body of the source side select transistor comprises:

forming crystalline silicon in the vertical memory hole.

14. The method of claim 12, wherein the forming silicon for the body of the source side select transistor comprises:

epitaxially growing crystalline silicon in the vertical memory hole upwards from the substrate.

15. The method of claim 12, wherein the introducing a dopant into the vertical opening and into the first horizontal recess to dope the body of the source side select transistor comprises one of:

performing gas phase doping;

performing monolayer doping;

or

performing plasma doping.

16. The method of claim 12, further comprising:

forming a conductive layer in the vertical opening down to the substrate, the conductive layer serving as a source line for the NAND string, wherein the source side select transistor couples the NAND string to the source line.

17. A method of fabricating non-volatile storage, the method comprising:

forming a stack of alternating layers of silicon oxide and silicon nitride over a substrate;

etching a plurality of memory holes through the alternating layers of silicon oxide and silicon nitride, the memory holes each having a vertical sidewall;

growing crystalline silicon in the plurality of memory holes upwards from the substrate, the crystalline silicon covers the vertical sidewalls of the memory holes near the substrate;

forming a memory cell film on the vertical sidewalls of the plurality of memory holes above the crystalline silicon;

etching a slit in the stack of alternating layers of silicon oxide and silicon nitride;

removing the layers of the silicon nitride to form recesses, a first recess of the recesses exposes the crystalline silicon;

introducing a dopant into the slit and into the first recess to dope the crystalline silicon;

forming a conductive material in the recesses, the conductive material in the recesses serving as word lines for NAND strings formed in the memory holes and as control gates for source side select transistors of the NAND strings; and

forming a conductive material in the slit down to the substrate, the conductive material in the slit down to the substrate serving as a source line for the NAND strings.

18. The method of fabricating non-volatile storage of claim 17, wherein the dopant that is introduced into the slit and into the first recess to dope the crystalline silicon is a first dopant having a first type of conductivity, further comprising:

introducing a second dopant having a second type of conductivity into the slit to dope the substrate below the slit.

19. The method of fabricating non-volatile storage of claim 18, wherein after introducing the second dopant into the slit to dope the substrate below the slit and after introducing the dopant into the slit and into the first recess to dope the crystalline silicon the substrate below the slit has a net doping of the second type of conductivity.

20. The method of fabricating non-volatile storage of claim 17, wherein the growing crystalline silicon in the plurality of memory holes upwards from the substrate, comprises:

epitaxially growing crystalline silicon up to a level above where the first recess will be formed, wherein the dopant is concentrated in the crystalline silicon near the level of the first recess and has a gradually lower concentration moving upwards from the level of the first recess.