Memory cell pillar including source junction plug

• US 9,780,102 B2
• Filed: 11/07/2014
• Issued: 10/03/2017
• Est. Priority Date: 11/07/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Simsek-Ege, Fatma Arzum, Parat, Krishna K., Tran, Luan C., Kuo, Meng-Wei, Hu, Yushi
• Primary Examiner(s): Kim, Su C
• Application Number:
  US14/536,021
• Publication Number:
  US 20160133638A1
• Time in Patent Office: 1,061 Days
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Claims

1. An apparatus comprising:

a source material;

a dielectric material over the source material, the dielectric material including an opening, the opening including a recess, the recess including a first recess sidewall and a second recess sidewall opposite from the first recess sidewall;

a select gate material over the dielectric material, the select gate material including an opening having a first side wall and a second sidewall opposite from the first sidewall;

a memory cell stack over the select gate material;

a conductive plug located in the opening including the recess of the dielectric material and contacting a portion of the source material, the conductive plug including an epitaxial material;

a channel material extending through the memory cell stack and through the select gate material between the first and second sidewalls of the select gate material and contacting the conductive plug, wherein a distance between the first and second recess sidewalk is greater than a distance between the first and second sidewalls of the opening of the select gate material; and

a metal combined with a semiconductor material, wherein the source material is between the dielectric material and the metal combined with the semiconductor material.

2. The apparatus of claim 1, wherein the dielectric material includes a dielectric constant greater than a dielectric constant of silicon dioxide.

3. The apparatus of claim 1, further comprising an additional dielectric material surrounded by at least a portion of the channel material.

4. The apparatus of claim 1, wherein the source material includes a conductively-doped polysilicon.

5. The apparatus of claim 1, further comprising a silicon nitride material between the channel material and the select gate material.

6. The apparatus of claim 5, further comprising silicon dioxide material between the channel material and the select gate material.

7. The apparatus of claim 1, further comprising oxide-nitride-oxide (ONO) material between the channel material and the select gate material.

8. The apparatus of claim 1, wherein the select gate material includes conductively-doped polysilicon.

9. The apparatus of claim 1, further comprising an additional dielectric material located in the recess and in between the conductive plug and the dielectric material over the source material.

11. The apparatus of claim 1, further comprising an additional select gate material over the memory cell stack.

10. An apparatus comprising:

a source material;

a dielectric material over the source material, the dielectric material including an opening;

a select gate material over the dielectric material;

a memory cell stack over the select gate material;

a conductive plug located in the opening of the dielectric material and contacting a portion of the source material;

a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug; and

a transition metal combined with a semiconductor material, wherein the source material is between the dielectric material and the transition metal combined with the semiconductor material.

12. An apparatus comprising:

a source material;

a first dielectric material over the source material, the first dielectric material including a dielectric constant greater than a dielectric constant of silicon dioxide;

a source-side select (SGS) gate material over the first dielectric material;

levels of memory cells over the SGS select gate material;

a cell pillar extending through the levels of memory cells, the SGS gate material, and the first dielectric material, the cell pillar including a conductive plug contacting the source material, the conductive plug including an epitaxial material, a channel material contacting the conductive plug, and a second dielectric material surrounded by at least a portion of the channel material; and

a metal combined with a semiconductor material, wherein the source material is between the dielectric material and the metal combined with the semiconductor material.

13. The apparatus of claim 12, wherein the conductive plug has a thickness of at least one-half of a thickness of the first dielectric material.

14. The apparatus of claim 12, wherein the first dielectric material has a thickness greater than 30 nanometers.

15. The apparatus of claim 12, wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material.

16. An apparatus comprising:

a source material;

a first dielectric material over the source material, the first dielectric material including a dielectric constant greater than a dielectric constant of silicon dioxide;

a source-side select (SGS) gate material over the first dielectric material;

levels of memory cells over the SGS select gate material;

a cell pillar extending through the levels of memory cells, the SGS gate material, and the first dielectric material, the cell pillar including a conductive plug contacting the source material, a channel material contacting the conductive plug, and a second dielectric material surrounded by at least a portion of the channel material; and

a substrate and a silicide material between the substrate and the source material.

17. A method comprising:

forming a source material;

forming a dielectric material over the source material;

forming a source-side select (SGS) gate material over the dielectric material;

forming alternating levels of materials over the SGS gate material;

forming a first portion of a cell pillar, the first portion of the cell pillar contacting the source material and located between the alternating levels of materials and the source material, wherein forming the first portion of the cell pillar includes growing an epitaxial material from a portion of the source material, such that the epitaxial material is part of the first portion of the cell pillar;

forming a second portion of the cell pillar after the first portion of the cell pillar is formed, the second portion of the cell pillar contacting the first portion of the cell pillar and extending through the alternating levels of materials; and

forming a metal combined with a semiconductor material, wherein the source material is between the dielectric material and the metal combined with the semiconductor material.

18. The method of claim 17, wherein the dielectric material has a dielectric constant greater than a dielectric constant of silicon dioxide.

19. The method of claim 17, further comprising:

introducing dopants into the first portion of the cell pillar; and

introducing dopants into the second portion of the cell pillar, wherein a concentration of the first dopants is different from a concentration of the second dopants.

20. The method of claim 17, wherein forming the alternating levels of materials includes forming a number of levels of conductor materials and a number of levels of dielectric materials.

21. The method of claim 17, further comprising:

forming levels of memory cells in the alternating levels of materials before forming the first portion of the cell pillar.

22. The method of claim 17, further comprising:

forming levels of memory cells in the alternating levels of materials after forming the first portion of the cell pillar.

23. The method of claim 17, further comprising:

forming an additional dielectric material in a space surrounded by part of the second portion of the cell pillar.

24. A method comprising:

forming a source material;

forming a dielectric material over the source material;

forming a select gate material over the dielectric material;

forming alternating levels of materials over the select gate material;

forming an opening through the alternating levels of materials, the select gate material, and the dielectric material, such that a portion of the source material is exposed through the opening;

forming a conductive plug contacting the portion of the source material that is exposed through the opening; and

forming a channel material extending through the alternating levels of materials and the select gate material and contacting the conductive plug, wherein forming the conductive plug includes growing an epitaxial material from the portion of the source material, such that the epitaxial material is part of the conductive plug.

25. The method of claim 24, further comprising:

introducing dopants into the epitaxial material while the epitaxial material is formed.

26. The method of claim 24, further comprising:

introducing dopants into the epitaxial material after the epitaxial material is formed.

27. The method of claim 24, wherein the dielectric material includes aluminum oxide.

28. The method of claim 24, further comprising:

forming a first additional dielectric material before forming the conductive plug, such that the first additional dielectric material is on a sidewall adjacent the select gate material and adjacent the dielectric material over the source material.

29. The method of claim 28, further comprising:

forming a second additional dielectric material on the first additional dielectric material, wherein the first and second additional dielectric materials are not removed after the channel material is formed.

30. The method of claim 29, further comprising:

forming a tunneling material between the channel material and the first and second additional dielectric materials.

31. The method of claim 24, wherein further comprising:

forming an additional dielectric material in a recess between the conductive plug and the dielectric material over the source material before forming the conductive plug.