Method of forming a semiconductor device including forming a shield conductor overlying a gate conductor

• US 9,780,196 B2
• Filed: 09/09/2016
• Issued: 10/03/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Venkatraman, Prasad, Grivna, Gordon M.
• Primary Examiner(s): Chang, Jay C
• Application Number:
  US15/261,308
• Publication Number:
  US 20160380079A1
• Time in Patent Office: 389 Days
• Field of Search: None
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Claims

1. A method of forming a semiconductor device comprising:

providing a multi-layer semiconductor material having a first layer of a first conductivity type, having a first region of a second conductivity type overlying the first layer, having a plurality of openings that extend from a surface of the first region into the first layer wherein the plurality of openings have sidewalls, a gate insulator formed on the sidewalls of a first opening of the plurality of openings, and a gate conductor material within the first opening;

removing a first portion of the gate conductor material from the first opening and leaving a second portion of the gate conductor material within the first opening as a gate conductor wherein a portion of the first layer that underlies the gate conductor forms a channel region of the semiconductor device;

forming a shield insulator within the first opening and overlying the gate conductor;

forming a shield conductor within the first opening overlying the gate conductor; and

forming a source conductor on a portion of the shield conductor to form an electrical connection between the shield conductor and the first layer.

2. The method of claim 1 further including forming a source contact conductor to extend through the first region and into the first layer including forming the source contact conductor after forming the shield conductor and before forming an electrical connection between the source conductor and the shield conductor.

3. The method of claim 1 further including forming a source region of the second conductivity type in the first layer and proximal to the gate conductor.

4. The method of claim 3 further including forming the source conductor to electrically contact the source region.

5. The method of claim 1 further including forming a source contact conductor to extend through the first region and into the first layer including forming the source contact conductor prior to removing the first portion of the gate conductor material from the first opening.

6. The method of claim 1 including forming the shield insulator covering a top surface of the gate conductor and insulating the shield conductor from electrically contacting the gate conductor.

7. The method of claim 1 including forming the shield conductor on the shield insulator.

8. The method of claim 1 wherein forming the source conductor on a portion of the shield conductor to form the electrical connection between the shield conductor and the first layer includes forming the source conductor on a portion of the shield conductor to form a direct electrical connection between the shield conductor and the first layer.

9. A method of forming a semiconductor device comprising:

providing a multi-layer semiconductor material having a first layer of a first conductivity type, having a first region of a second conductivity type overlying the first layer, having a plurality of openings that extend from a surface of the first region into the first layer wherein the plurality of openings have sidewalls, a gate insulator formed on the sidewalls of a first opening of the plurality of openings, and a gate conductor material within the first opening;

removing a first portion of the gate conductor material from the first opening and leaving a second portion of the gate conductor material within the first opening as a gate conductor wherein a portion of the first layer that underlies the gate conductor forms a channel region of the semiconductor device;

forming a shield insulator within the first opening and overlying the gate conductor including forming the shield insulator with a second opening within the shield insulator with at least a portion of the second opening extending substantially parallel to the sidewalls of the first opening, and forming a shield conductor within the portion of the second opening;

forming the shield conductor overlying the gate conductor; and

forming a source conductor on a portion of the shield conductor to form an electrical connection between the shield conductor and the first layer.