Method and structure of forming self-aligned RMG gate for VFET

• US 9,780,208 B1
• Filed: 07/18/2016
• Issued: 10/03/2017
• Est. Priority Date: 07/18/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Park, Chanro, Sung, Min Gyu, Kim, Hoon
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Tang, Sue
• Application Number:
  US15/212,755
• Time in Patent Office: 442 Days
• Field of Search: 257329
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

Claims

1. A method comprising:

providing a fin structure comprising a fin with sacrificial material above and adjacent the fin, the fin structure being above a substrate adjacent a source or drain;

removing a first portion of the sacrificial material above the fin to form an opening within the sacrificial material on top of the fin;

forming a top source or drain within the opening on top of the fin;

removing a second portion of the sacrificial material adjacent the top source or drain;

depositing a spacer above and adjacent the top source or drain;

removing the remaining sacrificial material;

depositing a gate material above the spacer and below the spacer to the sides of the fin; and

removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and a vertical field effect transistor.

2. The method of claim 1, wherein the sacrificial material comprises a first sacrificial material.

3. The method of claim 2, wherein a top portion of the first sacrificial material located above and adjacent said fin structure is removed to allow a remaining portion of the first sacrificial material to remain adjacent said fin.

4. The method of claim 3, wherein a second sacrificial material is deposited above the remaining first sacrificial material wherein the sacrificial material comprises a first sacrificial material, the second sacrificial material, and a hard mask on the top of said fin.

5. The method of claim 4, wherein the first sacrificial material comprises a thin oxide surrounding said fin structure and an amorphous silicon deposited on top of said thin oxide.

6. The method of claim 5, wherein the second sacrificial material comprises an oxide.

7. The method of claim 6, wherein removing a first portion of the sacrificial material above the fin form an opening within the sacrificial material on top of the fin comprises removing the hard mask above or on top of said fin.

8. The method of claim 7, wherein a self-aligned contact (SAC) cap is deposited above the top source or drain within said oxide.

9. The method of claim 8, further comprising removing the oxide prior to the step of depositing a spacer above and adjacent the top source or drain.

10. The method of claim 9, wherein removing a third portion of the sacrificial material adjacent the fin comprises removing the amorphous silicon.

11. The method of claim 10, further comprising removing the thin oxide.

12. The method of claim 11, wherein the thin oxide comprises a silicon oxide.

13. The method of claim 12, further comprising providing a bottom spacer above said source or drain and substrate adjacent said fin.

14. The method of claim 13, further comprising depositing a high K dielectric material on said bottom spacer, said spacer and said fin to form an intermediate structure and annealing said intermediate structure.

15. The method of claim 14, further comprising depositing a work function metal as part of said gate material and a metal over said work function metal as part of said gate material.

16. The method of claim 15, wherein removing the gate material above the bottom portion of the spacer comprises removing said work function metal and said metal.

17. The method of claim 16, further comprising removing annealed high K material above said spacer above and adjacent the top source or drain;

depositing a second lithography stack over the barrier stack;

performing a second lithography to pattern the at least one via opening; and

etching to form the at least one via opening.

18. The method of claim 17, wherein the method comprises providing multiple fin structures, multiple top sources or drains to form multiple vertical field effect transistors parallel spaced with at least two vertical field effect transistors spaced apart and aligned along lengths thereof and forming at least one additional gate connecting aligned on parallel spaced vertical field effect transistors.

19. A method comprising:

providing a fin structure comprising a fin with a hard mask on top of the fin, the fin structure being above a substrate adjacent a source or drain;

depositing one or more sacrificial materials above and along sides of the fin structure;

removing a top portion of the one or more sacrificial materials above a top of the fin to form an opening within the one or more sacrificial materials;

forming a top source or drain within the opening on the top of said fin;

removing a portion of the one or more sacrificial materials above and adjacent the top source or drain;

depositing a spacer above the top source or drain;

removing additional portions of the one or more sacrificial materials surrounding sides of the fin;

depositing gate material above the spacer and below the spacer to the sides of the fin; and

removing the gate material above the bottom portion of the spacer to form a self aligned gate around the fin and vertical field effort transistor.