Combination FinFET and methods of forming same

• US 9,780,216 B2
• Filed: 03/19/2014
• Issued: 10/03/2017
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Perng, Tsu-Hsiu, Lee, Tung Ying, Tsai, Ming-Huan, Wann, Clement Hsingjen
• Primary Examiner(s): Prenty, Mark
• Application Number:
  US14/219,869
• Publication Number:
  US 20150270401A1
• Time in Patent Office: 1,294 Days
• Field of Search: 438283
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.

Claims

1. A fin field effect transistor (finFET) comprising:

a fin extending upwards from a semiconductor substrate; and

a gate stack disposed over and covering sidewalls of a channel region of the fin, wherein the channel region comprises a first semiconductor material and at least a portion of a second semiconductor material, the first semiconductor material different from the second semiconductor material, wherein the second semiconductor material contacts both the gate stack and a shallow trench isolation (STI) region, wherein an interface of the gate stack and the first semiconductor material has a higher interface trap density than an interface of the gate stack and the second semiconductor material, wherein the channel region further comprises an inter-diffusion region.

2. The finFET of claim 1, wherein the first semiconductor material has a first vertical dimension and the channel region has a second vertical dimension, and wherein a ratio of the first vertical dimension to the second vertical dimension is at least about 0.6.

3. The finFET of claim 1, wherein an atomic percentage of germanium in the first semiconductor material is at least about ten percent.

4. The finFET of claim 1, wherein the first semiconductor material is germanium, silicon germanium, indium gallium arsenic, or silicon germanium tin.

5. The finFET of claim 1, wherein the second semiconductor material is silicon, silicon germanium, or silicon germanium tin.

6. The finFET of claim 1, wherein the fin further comprises a third semiconductor material, the third semiconductor material different from the first semiconductor material and the second semiconductor material.

7. The finFET of claim 1, wherein a first horizontal dimension of the first semiconductor material is wider than a second horizontal dimension of an interface between the first semiconductor material and the second semiconductor material.

20. The finFET of claim 1, wherein a first horizontal dimension of the first semiconductor material is less than a second horizontal dimension of an interface between the first semiconductor material and the second semiconductor material.

8. A semiconductor device comprising:

a first shallow trench isolation (STI) region over a substrate;

a first semiconductor strip over the substrate;

a second STI region over the substrate, the first semiconductor strip disposed between the first STI region and the second STI region, a top surface of the first STI region being lower than a top surface of the second STI region;

a second semiconductor strip over the first semiconductor strip, wherein the first and the second semiconductor strips comprise different semiconductor materials;

a channel region, wherein the channel region comprises the second semiconductor strip and at least a portion of the first semiconductor strip, and wherein a ratio of a first vertical dimension of the second semiconductor strip to a second vertical dimension of the channel region is at least 0.6; and

a gate stack over and covering sidewalls of the channel region.

9. The semiconductor device of claim 8, wherein the first semiconductor strip comprises a first semiconductor material and the second semiconductor strip comprises a second semiconductor material, wherein the second semiconductor material has a higher mobility than the first semiconductor material, and wherein the first semiconductor material has a lower interface trap density than the second semiconductor material.

10. The semiconductor device of claim 9, wherein the top surface of the first STI region is lower than a top surface of the first semiconductor strip.

11. The semiconductor device of claim 9, wherein the top surface of the first STI region is concave.

12. The semiconductor device of claim 9, wherein the top surface of the first STI region is convex.

18. The semiconductor device of claim 8, wherein a first horizontal dimension of the second semiconductor strip is wider than a second horizontal dimension of an interface between the first semiconductor strip and the second semiconductor strip.

19. The semiconductor device of claim 8, wherein a first horizontal dimension of the second semiconductor strip is narrower than a second horizontal dimension of an interface between the first semiconductor strip and the second semiconductor strip.

13. A semiconductor device comprising:

a fin extending upward from a semiconductor substrate, wherein the fin comprises;

a first semiconductor material;

a second semiconductor material over the first semiconductor material, wherein the second semiconductor material comprises a higher mobility and a higher interface trap density than the first semiconductor material; and

a third semiconductor material under and different than the first semiconductor material; and

a gate stack over the fin, extending along sidewalls of the second semiconductor material, and extending at least partially along sidewalls of the first semiconductor material, wherein the gate stack comprises;

a gate dielectric; and

a gate electrode over the gate dielectric; and

a shallow trench isolation (STI) region, the STI region extending along remaining portions of the sidewalls of the first semiconductor material not extending along the gate stack.

14. The semiconductor device of claim 13, wherein a portion of the fin wrapped by the gate stack defines a channel region of the fin, and wherein a vertical dimension of the second semiconductor material is at least sixty percent of a vertical dimension of the channel region of the fin.

15. The semiconductor device of claim 13, wherein an interface between the third semiconductor material and the first semiconductor material is substantially level.

16. The semiconductor device of claim 13, wherein an interface between the third semiconductor material and the first semiconductor material is concave or convex.

17. The semiconductor device of claim 13, wherein an interface between the first semiconductor material and the second semiconductor material has an inter-diffusion region.