Combination FinFET and methods of forming same
First Claim
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1. A fin field effect transistor (finFET) comprising:
- a fin extending upwards from a semiconductor substrate; and
a gate stack disposed over and covering sidewalls of a channel region of the fin, wherein the channel region comprises a first semiconductor material and at least a portion of a second semiconductor material, the first semiconductor material different from the second semiconductor material, wherein the second semiconductor material contacts both the gate stack and a shallow trench isolation (STI) region, wherein an interface of the gate stack and the first semiconductor material has a higher interface trap density than an interface of the gate stack and the second semiconductor material, wherein the channel region further comprises an inter-diffusion region.
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Abstract
An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.
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Citations
20 Claims
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1. A fin field effect transistor (finFET) comprising:
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a fin extending upwards from a semiconductor substrate; and a gate stack disposed over and covering sidewalls of a channel region of the fin, wherein the channel region comprises a first semiconductor material and at least a portion of a second semiconductor material, the first semiconductor material different from the second semiconductor material, wherein the second semiconductor material contacts both the gate stack and a shallow trench isolation (STI) region, wherein an interface of the gate stack and the first semiconductor material has a higher interface trap density than an interface of the gate stack and the second semiconductor material, wherein the channel region further comprises an inter-diffusion region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 20)
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8. A semiconductor device comprising:
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a first shallow trench isolation (STI) region over a substrate; a first semiconductor strip over the substrate; a second STI region over the substrate, the first semiconductor strip disposed between the first STI region and the second STI region, a top surface of the first STI region being lower than a top surface of the second STI region; a second semiconductor strip over the first semiconductor strip, wherein the first and the second semiconductor strips comprise different semiconductor materials; a channel region, wherein the channel region comprises the second semiconductor strip and at least a portion of the first semiconductor strip, and wherein a ratio of a first vertical dimension of the second semiconductor strip to a second vertical dimension of the channel region is at least 0.6; and a gate stack over and covering sidewalls of the channel region. - View Dependent Claims (9, 10, 11, 12, 18, 19)
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13. A semiconductor device comprising:
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a fin extending upward from a semiconductor substrate, wherein the fin comprises; a first semiconductor material; a second semiconductor material over the first semiconductor material, wherein the second semiconductor material comprises a higher mobility and a higher interface trap density than the first semiconductor material; and a third semiconductor material under and different than the first semiconductor material; and a gate stack over the fin, extending along sidewalls of the second semiconductor material, and extending at least partially along sidewalls of the first semiconductor material, wherein the gate stack comprises; a gate dielectric; and a gate electrode over the gate dielectric; and a shallow trench isolation (STI) region, the STI region extending along remaining portions of the sidewalls of the first semiconductor material not extending along the gate stack. - View Dependent Claims (14, 15, 16, 17)
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Specification