Methods and apparatus for standard protocol validation mechanisms deployed over a switch fabric system

• US 9,781,009 B2
• Filed: 08/31/2016
• Issued: 10/03/2017
• Est. Priority Date: 12/29/2010
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Mehra, Ashwani Kumar, Rajamani, Srikar, Saksena, Saurabh
• Primary Examiner(s): Lai, Andrew
• Assistant Examiner(s): LEE, ANDREW CHUNG CHEUNG
• Application Number:
  US15/252,957
• Publication Number:
  US 20160373307A1
• Time in Patent Office: 398 Days
• CPC Class Codes: H04L 41/0654 using network fault recovery ring fault isolation or reconfiguration in loop networks without recovery actions by a network management system H04L12/437
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 43/04 Processing captured monitoring data, e.g. for logfile generation
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: H04L 45/24 Multipath
• CPC Class Codes: H04L 45/28 using route fault recovery
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04W 24/08 Testing, supervising or monitoring using real traffic

Abstract

An apparatus includes a destination edge device configured to receive a first validation packet according to a switch fabric validation protocol. The destination edge device is configured to validate multiple data paths through a distributed switch fabric from a source edge device to the destination edge device based on the first validation packet. The destination edge device is configured to send, in response to receiving the first validation packet, a second validation packet to a peripheral processing device. The destination edge device is also configured to send the second validation packet according to a validation protocol different from the first validation protocol.

Claims

1. An apparatus, comprising:

a memory; and

a processor operatively coupled to the memory, the processor configured to determine a set of available output ports through which a validation packet can be sent to reach a destination device, the processor configured to encapsulate, for each available output port of the set of available output ports, header information in the validation packet, and information relating to that available output port, to produce a validation packet header,

the processor configured to generate, for each available output port of the set of available output ports, a replicated validation packet including the validation packet header and being one of a plurality of replicated validation packets, each replicated validation packet from the plurality of replicated validation packets uniquely corresponding to an available output port from the set of available output ports; and

the processor configured to cause the plurality of replicated validation packets to be sent to the destination device, using the set of available output ports and based on the validation packet header of each replicated validation packet from the plurality of replicated validation packets.

2. The apparatus of claim 1, wherein the set of available output ports is determined based on information in the validation packet.

3. The apparatus of claim 1, wherein the validation packet header of each replicated validation packet in the plurality of replicated validation packets includes a value from a reverse hash lookup table that includes an association between a hash function input value and an identifier of the output port uniquely corresponding to that replicated validation packet.

4. The apparatus of claim 1, wherein the validation packet header of each replicated validation packet in the plurality of replicated validation packets includes a unique hash index value representing an index to a table of link aggregation group (LAG) members, the table including a value associated with the destination device.

5. The apparatus of claim 1, wherein the is configured to input a value from each validation packet header of each replicated validation packet in the plurality of replicated validation packets into a hash function, the processor configured to determine an output port to which to send each replicated validation packet in the plurality of replicated validation packets based on outputs of the hash function.

6. The apparatus of claim 1, wherein the validation packet is defined according to one of an IEEE 802.1ag protocol;

a virtual private local area network service (VPLS) protocol;

an international telecommunications union (ITU) Y.1731 protocol, or a multiprotocol label switching transport profile (MPLS-TP) operations, administration and management/maintenance (OAM) protocol.

7. The apparatus of claim 1, wherein the validation packet causes a processor to detect a network failure based on the validation packet.

8. A method, comprising:

receiving, at a destination device, a signal indicating that a set of switch fabric validation packets will be sent through a switch fabric system;

receiving, at the destination device, a predetermined schedule of when the set of switch fabric validation packets will be sent; and

when a first subset of the set of switch fabric validation packets is not received at the destination device and a second subset of the set of switch fabric validation packets is received;

consolidating, at the destination device, the second subset of the set of switch fabric validation packets into a consolidated switch fabric validation packet including a status state indicator indicating a status of each data path of a plurality of data paths, each data path of the plurality of data paths being associated with a switch fabric validation packet from the first subset of the set of switch fabric validation packets; and

sending, from the destination device, the consolidated switch fabric validation packet to a validation gateway.

9. The method of claim 8, wherein a network failure is detected based on not receiving the first subset of the set of switch fabric validation packets.

10. The method of claim 8, wherein the status indicates whether a data path from the plurality of data paths is operational or not operational.

11. The method of claim 8, wherein the status state indicator indicates that a set of data paths over which the first subset of the set of switch fabric validation packets were sent are not operational.

12. The method of claim 8, wherein the status state indicator indicates that a set of data paths over which the second subset of the set of switch fabric validation packets were sent are operational.

13. The method of claim 8, wherein the status state indicator includes a percentage of expected packets that were actually received at the destination device.

14. The method of claim 8, further comprising sending a validation data packet that includes the status state indicator to a destination peripheral processing device.

15. An apparatus, comprising:

a memory storing processor-readable instructions; and

a fabric validation (FV) processor operatively coupled to the memory and configured to execute the processor-readable instructions, the FV processor configured, in response to executing the processor-readable instructions, to receive a set of switch fabric validation packets from a source device, the FV processor configured, in response to executing the processor-readable instructions, to compare the set of switch fabric validation packets to a preset schedule indicating a timing and a number of switch fabric validation packets to be received at the FV processor,

the FV processor configured, in response to executing the processor-readable instructions, to consolidate the set of switch fabric validation packets into a consolidated switch fabric validation packet,

the FV processor configured, in response to executing the processor-readable instructions, to append, to the consolidated switch fabric validation packet and when a switch fabric validation packet indicated in the preset schedule is not included in the set of switch fabric validation packets from the source device, a status state indicator indicating a status of at least one data path between the FV processor and the source device, to produce an appended consolidated switch fabric validation packet,

the FV processor configured, in response to executing the processor-readable instructions, to send the appended consolidated switch fabric validation packet to a validation gateway.

16. The apparatus of claim 15, wherein a network failure is detected based on not receiving each of the switch fabric validation packets indicated in the preset schedule.

17. The apparatus of claim 15, wherein the status state indicator indicates that a set of data paths over which a portion of the set of switch fabric validation packets were sent are not operational.

18. The apparatus of claim 15, wherein the status state indicator indicates that a set of data paths over which a portion of the set of switch fabric validation packets were sent are operational.

19. The apparatus of claim 15, wherein the status state indicator includes a percentage of expected packets that were actually received at the FV processor.

20. The apparatus of claim 15, wherein the FV processor is configured, in response to executing the processor-readable instructions, to send a validation data packet that includes the status state indicator to a destination peripheral processing device.