Systems and methods to communicate with external destinations via a memory network

• US 9,781,027 B1
• Filed: 04/02/2015
• Issued: 10/03/2017
• Est. Priority Date: 04/06/2014
• Status: Active Grant

• Current Assignee: DataRobot, Inc.
• Original Assignee: Parallel Machines Ltd.
• Inventors: Braverman, Avner, Shalvi, Ofir, Khermosh, Lior, Bar-Or, Ofer, Oren, Eyal Benjamin Raz, Zuckerman, Gal
• Primary Examiner(s): Tokuta, Shean
• Application Number:
  US14/676,937
• Time in Patent Office: 915 Days
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

Various systems and methods to facilitate general communication, via a memory network, between compute elements and external destinations, while at the same time facilitating low latency communication between compute elements and memory modules storing data sets, without impacting negatively the latency of the communication between the compute elements and the memory modules. General communication messages between compute nodes and a gateway compute node are facilitated with a first communication protocol adapted for low latency transmissions. Such general communication messages are then transmitted to external destinations with a second communication protocol that is adapted for the general communication network and which may or may not be low latency, but such that the low latency between the compute elements and the memory modules is not negatively impacted. The memory modules may be based on RAM or DRAM or another structure allowing low latency access by the compute elements.

Claims

1. A system operative to communicate with destinations external to the system via a memory network, comprising:

a gateway compute node;

a plurality of compute elements; and

a memory network comprising;

a shared memory pool configured to store a plurality of data sets; and

a switching network;

wherein;

said plurality of compute elements are configured to access said plurality of data sets via said switching network using a first communication protocol adapted for low latency transmissions, thereby resulting in said memory network having a first latency performance in conjunction with said access; and

said gateway compute node is configured to;

obtain, from said plurality of compute nodes, via said memory network, using said first communication protocol or another communication protocol adapted for low latency transmissions, a plurality of general communication messages intended for a plurality of destinations external to the system; and

transmit said plurality of general communication messages to said plurality of destinations external to the system, via a general communication network, using a second communication protocol adapted for said general communication network, in which said adaptation is facilitated by network functionality not available with the first communication protocol or with the another communication protocol, thereby achieving said communication with said destinations via said memory network, while simultaneously achieving, using said memory network, said access to said plurality of data sets in conjunction with said first latency performance;

wherein said switching network is a switching network selected from a group consisting of;

(i) a non-blocking switching network, (ii) a fat tree packet switching network, and (iii) a cross-bar switching network, thereby facilitating said access being simultaneous in conjunction with at least some of said plurality of data sets, wherein at least one of the data sets is accessed simultaneously with at least another of the data sets, thereby preventing delays associated with said access, thereby further facilitating said first latency performance in conjunction with said first communication protocol.

2. A system operative to communicate with destinations external to the system via a memory network, comprising:

a gateway compute node;

a plurality of compute elements; and

a memory network comprising;

a shared memory pool configured to store a plurality of data sets; and

a switching network;

wherein;

said plurality of compute elements are configured to access said plurality of data sets via said switching network using a first communication protocol adapted for low latency transmissions, thereby resulting in said memory network having a first latency performance in conjunction with said access; and

said gateway compute node is configured to;

obtain, from said plurality of compute nodes, via said memory network, using said first communication protocol or another communication protocol adapted for low latency transmissions, a plurality of general communication messages intended for a plurality of destinations external to the system; and

transmit said plurality of general communication messages to said plurality of destinations external to the system, via a general communication network, using a second communication protocol adapted for said general communication network, in which said adaptation is facilitated by network functionality not available with the first communication protocol or with the another communication protocol,

thereby achieving said communication with said destinations via said memory network, while simultaneously achieving, using said memory network, said access to said plurality of data sets in conjunction with said first latency performance;

wherein said shared memory pool comprises a plurality of memory modules associated respectively with a plurality of data interfaces communicatively connected with said switching network, in which the plurality of data sets are distributed among the plurality of memory modules, wherein each data interface is configured to extract from the respective memory module the respective data set simultaneously with another of the data interfaces extracting from the respective memory module the respective data set, and wherein, as a result, at least one of the data sets is transported to one of said compute elements, in conjunction with said access, simultaneously with at least another of the data sets transported to another of said compute elements in conjunction with said access, thereby preventing delays associated with said access, thereby further facilitating said first latency performance in conjunction with said first communication protocol.

3. The system of claim 2, wherein said memory modules are based on random-access-memory (RAM), in which said extraction is performed using random access read cycles, thereby further facilitating said first latency performance in conjunction with said first communication protocol.

4. The system of claim 3, wherein said memory modules are based on dynamic-random-access-memory (DRAM), in which said extraction is done in less than 2 (two) microseconds, and said access is done in less than 5 (five) microseconds.

5. The system of claim 2, wherein said obtaining comprises:

writing, by said compute elements, said general communication messages into said memory modules; and

reading, by said gateway compute node, said general communication messages from said memory modules.

6. The system of claim 5, wherein said writing comprises:

sending, by one of said compute element, to one of said data interfaces, via said switching network, using a packetized message associated with said first communication protocol, one of the general communication messages; and

writing said one of the general communication messages, by said one of the data interfaces, to the associated memory module, using a random-access write cycle.

7. The system of claim 6, wherein said reading comprises:

reading said one of the general communication messages, by said one of the data interfaces, from the associated memory module, using a random-access read cycle; and

sending, by said one of the data interfaces, to the gateway compute node, via said switching network, using a packetized message associated with said first communication protocol, said one of the general communication messages.

8. The system of claim 2, wherein:

said first communication protocol is a layer two (L2) communication protocol, in which layer three (L3) traffic is absent from said memory network, thereby facilitation said first latency performance; and

said second communication protocol is a layer three (L3) communication protocol, in which layer three functionality is added by said gateway compute element to said general communication messages, thereby facilitating said transmission to those of the destinations that require layer three functionality such as Internet-Protocol (IP) addressing functionality.

9. The system of claim 2, wherein:

said first communication protocol does not include a transmission control protocol (TCP), thereby facilitating said first latency performance; and

said second communication protocol includes a transmission control protocol, in which relevant handshaking is added by said gateway compute element in conjunction with said general communication messages when relaying said general communication messages to those destinations requiring a transmission control protocol.

10. The system of claim 2, wherein said switching network is based on Ethernet.

11. The system of claim 10, wherein said general communication network is at least one network of Internet.

15. The system of claim 2, wherein said obtaining comprises sending by the compute elements said general communication messages to said gateway compute node using a packetized transmission associated with said first communication protocol directly via said switching network.

16. The system of claim 2, further comprising:

a first server;

a second server; and

a third server,

wherein;

at least one of the compute nodes is located in said first server;

at least a part of the shared memory pool is located inside said second server;

said gateway compute node is located inside said third server; and

said switching network is located outside said first, second, and third servers,

thereby said memory network facilitates memory disaggregation in said system.

12. A system operative to communicate with destinations external to the system via a memory network, comprising:

a gateway compute node;

a plurality of compute elements; and

a memory network comprising;

a shared memory pool configured to store a plurality of data sets; and

a switching network;

wherein;

said plurality of compute elements are configured to access said plurality of data sets via said switching network using a first communication protocol adapted for low latency transmissions, thereby resulting in said memory network having a first latency performance in conjunction with said access; and

said gateway compute node is configured to;

obtain, from said plurality of compute nodes, via said memory network, using said first communication protocol or another communication protocol adapted for low latency transmissions, a plurality of general communication messages intended for a plurality of destinations external to the system; and

transmit said plurality of general communication messages to said plurality of destinations external to the system, via a general communication network, using a second communication protocol adapted for said general communication network, in which said adaptation is facilitated by network functionality not available with the first communication protocol or with the another communication protocol, thereby achieving said communication with said destinations via said memory network, while simultaneously achieving, using said memory network, said access to said plurality of data sets in conjunction with said first latency performance;

wherein said shared memory pool is a key-value-store, in which said plurality of data sets are a plurality of values associated respectively with a plurality of keys.

13. The system of claim 12, further comprising a shared input-output medium associated with a medium controller, in which both the shared input-output medium and the medium controller are associated with one of the compute elements,

wherein:

said access is a high priority key-value transaction;

said one of the compute elements, in conjunction with said first communication protocol, is configured to initiate said high priority key-value transaction in conjunction with said key-value-store via said shared input-output medium; and

the medium controller, in conjunction with said first communication protocol, is configured to block lower priority transactions via said shared input-output medium during at least parts of said high priority key-value transactions, thereby preventing delays in said access, thereby further facilitating said first latency performance.

14. The system of claim 13, wherein said shared input-output medium is said switching network.