Sample and hold circuitry for monitoring voltages in an implantable neurostimulator

• US 9,782,588 B2
• Filed: 02/03/2017
• Issued: 10/10/2017
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Shi, Jess W., Feldman, Emanuel, Parramon, Jordi
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): Nguyen, Trung
• Application Number:
  US15/424,274
• Publication Number:
  US 20170143970A1
• Time in Patent Office: 249 Days
• Field of Search: 324600, 324691-693, 324702-710, 324676, 324 7611, 324 7677, 324323, 324360, 324120, 607 4, 607 5, 607 9, 607 55, 607 56, 607 57, 607 72- 74, 607 34, 607 66, 607119-123
• CPC Class Codes: A61B 5/24 Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: A61N 1/3937 Monitoring output parameters

Abstract

Sample and hold circuitry for monitoring electrodes and other voltages in an implantable neurostimulator is disclosed. The sample and hold circuitry in one embodiment contains multiplexers to selected appropriate voltages and to pass them to two storage capacitors during two different measurement phases. The capacitors are in a later stage serially connected to add the two voltages stored on the capacitors, and voltages present at the top and bottom of the serial connection are then input to a differential amplifier to compute their difference. The sample and hold circuitry is particularly useful in calculating the resistance between two electrodes, and is further particularly useful when resistance is measured using a biphasic pulse. The sample and hold circuitry is flexible, and can be used to measure other voltages of interest during biphasic or monophasic pulsing.

Claims

1. Circuitry for an implantable stimulator device, comprising:

stimulation circuitry comprising a first output and a second output;

a first decoupling capacitor between the first output and a first electrode configured to contact tissue of a patient, and a second decoupling capacitor between the second output and a second electrode configured to contact the tissue of the patient,

wherein the stimulation circuitry is configured to provide a stimulation pulse to the first output and the second output to cause current to flow through the first and second decoupling capacitors and through the patient'"'"'s tissue, wherein a parasitic voltage is formed across the first and second decoupling capacitors during the stimulation pulse; and

measurement circuitry configured to receive at least one output voltage at the first output and at least one output voltage at the second output during the stimulation pulse, wherein the measurement circuitry is configured to determine a resistance of the patient'"'"'s tissue using the output voltages, wherein the measurement circuit is further configured to cancel the parasitic voltages from the resistance determination.

2. The circuitry of claim 1, wherein the stimulation pulse comprises a biphasic pulse with a first and second pulse phase.

3. The circuitry of claim 2, wherein the measurement circuitry is configured to receive a first output voltage at the first output and a second output voltage at the second output during the first pulse phase, and wherein the measurement circuitry is configured to receive a third output voltage at the first output and a fourth output voltage at the second output during the second pulse phase.

4. The circuitry of claim 3, wherein the measurement circuitry is configured to determine a resistance of the patient'"'"'s tissue using the first, second, third, and fourth output voltages.

5. The circuitry of claim 4, wherein a first and second parasitic voltage is respectively formed across the first and second decoupling capacitors during the first pulse phase, and wherein a third and fourth parasitic voltage is respectively formed across the first and second decoupling capacitors during the second pulse phase.

6. The circuitry of claim 5, wherein the measurement circuit is further configured to cancel the first, second, third, and fourth parasitic voltages from the resistance determination.

7. The circuitry of claim 6, wherein the sum of the first and second parasitic voltages, and the sum of third and fourth parasitic voltages, equals zero.

8. The circuitry of claim 2, wherein the first and second pulse phases are of opposite polarity.

9. The circuitry of claim 3, wherein the measurement circuitry stores a first voltage difference between the first and second output voltages, and stores a second voltage difference between the third and fourth output voltages.

10. The circuitry of claim 9, wherein the resistance is determined by summing the first and second voltages differences, which sum cancels the parasitic voltages from the resistance determination and is indicative of the resistance of the patent'"'"'s tissue.

11. The circuitry of claim 1, wherein an amplitude of the stimulation pulse comprises I amps.

12. The circuitry of claim 11, wherein the measurement circuitry is configured to determine a resistance R of the patient'"'"'s tissue by determining a value 2IR, wherein I comprises an amplitude of the stimulation pulse.

13. The circuitry of claim 2, wherein an amplitude of the stimulation pulse during the first pulse phase comprises +I amps, and wherein an amplitude of the stimulation pulse during the second pulse phase comprises −

I amps.

14. The circuitry of claim 13, wherein the measurement circuitry is configured to determine a resistance R of the patient'"'"'s tissue by determining a value 2IR.

15. The circuitry of claim 3, wherein the measurement circuitry comprises a first storage capacitor configured to store a first difference between the first output voltage and the second output voltage, and a second storage capacitor configured to store a second difference between the third output voltage and the second output voltage.

16. The circuitry of claim 15, wherein the measurement circuit further comprises switching circuitry to sum the first difference and the second difference, wherein the sum cancels the parasitic voltages from the resistance determination and is indicative of the resistance of the patent'"'"'s tissue.

17. Circuitry for an implantable stimulator device, comprising:

stimulation circuitry configured to provide a first stimulation pulse with a first pulse phase and a second pulse phase from a first output to a first electrode configured to contact tissue of a patient, and to simultaneously provide a second stimulation pulse with a first pulse phase and a second pulse phase from a second output to a second electrode configured to contact tissue of the patient;

a first capacitor between the first output and the first electrode, and a second capacitor between the second output and the second electrode, wherein first and second parasitic voltages are respectively formed across the first and second capacitors during the first and second pulse phases; and

measurement circuitry configured to receive a first output voltage at the first output and a second output voltage at the second output during both of the first and second pulse phases, wherein the measurement circuitry is configured to determine a resistance of the patient'"'"'s tissue using the received first and second output voltages, wherein the measurement circuit is further configured to cancel the first and second parasitic voltages from the resistance determination.

18. The circuitry of claim 17, wherein a first sum of the first and second parasitic voltages during the first pulse phase equals the opposite of second sum of the first and second parasitic voltages during the second pulse phase, and wherein the measurement circuit sums the first and second sums to cancel the first and second parasitic voltages from the resistance determination.

19. The circuitry of claim 17, wherein the first stimulation pulse and the second stimulation pulse are of opposite polarity.

20. The circuitry of claim 19, wherein an amplitude of the first stimulation pulse comprises +I amps, and wherein an amplitude of the second stimulation pulse comprises −

I amps.