Taps of different scan classes with, without topology selection logic

• US 9,784,792 B2
• Filed: 11/10/2016
• Issued: 10/10/2017
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/348,352
• Publication Number:
  US 20170059653A1
• Time in Patent Office: 334 Days
• Field of Search: 714726, 714727, 714729
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Claims

1. An integrated circuit comprising:

(a) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead;

(b) a first test access port having a clock input connected to the first test clock lead and being free of the second test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the first test access port having class T0-T2 capabilities and being free of any topology selection logic;

(c) a second test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the second test access port including topology selection logic, being coupled in a series branch, and having class T0-T3, T4(W), T5(W) capabilities; and

(d) a third test access port having a clock input connected to the second test clock lead and being free of the first test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out lead, the third test access port including topology selection logic, being coupled in a Star-4 branch, having no class T0-T2 capabilities, and having class T3, T4(W), and T5(W) capabilities.

2. The integrated circuit of claim 1 including an external debug test system coupled to the first test clock lead, the second test clock lead, the test mode select lead, the test data in lead, and the test data out lead.