Maintaining synchronization during vertical blanking

• US 9,785,184 B2
• Filed: 08/24/2015
• Issued: 10/10/2017
• Est. Priority Date: 12/18/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ERDMAN, CHAD G
• Application Number:
  US14/833,424
• Publication Number:
  US 20150362947A1
• Time in Patent Office: 778 Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Claims

1. An apparatus, comprising:

a source processor configured to transmit data via a primary link; and

a sink processor coupled to the source processor via the primary link and a secondary link, wherein the sink processor is configured to receive the data via the primary link;

wherein the source processor is further configured to;

in response to a determination that operation of the primary link has been terminated;

pre-charge the secondary link to a particular voltage level;

send a signal to resume operation on the primary link to the sink processor, the signal including a preamble followed by a link clock frequency change command, wherein the preamble includes a number of consecutive logic values; and

send at least one clock recovery parameter to the sink processor.

2. The apparatus of claim 1, wherein the at least one clock recovery parameter includes a number of clock recovery symbols to perform clock data recovery.

3. The apparatus of claim 2, wherein the source processor is further configured to send the at least one clock recovery parameter via the primary link.

4. The apparatus of claim 1, wherein the source processor is further configured to send the signal to resume operation via the secondary link.

5. The apparatus of claim 1, wherein the source processor is further configured to send, to the sink processor, a number of symbols to use in training the primary link.

6. The apparatus of claim 5, wherein the source processor is further configured to send a number of lines to wait before resuming operation to the sink processor.

7. A method, comprising:

in response to determining that operation of a primary link between a first processor and a second processor has been terminated, wherein the second processor is coupled to a display;

pre-charging an auxiliary link between the first and second processors to a particular voltage level;

sending a signal to resume operation on the primary link from the first processor to the second processor, wherein the signal to resume operation includes a preamble followed by a link clock frequency change command, and wherein the preamble includes a number of consecutive logic values; and

sending, by the first processor, at least one clock recovery parameter to the second processor.

8. The method of claim 7, wherein the at least one clock recovery parameter includes a number of clock recovery symbols to perform clock data recovery.

9. The method of claim 7, further comprising sending the at least one clock recovery parameter via the primary link.

10. The method of claim 7, further comprising sending the signal to resume operation from the first processor to the second processor via the auxiliary link.

11. The method of claim 7, further comprising sending, by the first processor, a number of symbols to use in training to the primary link to the second processor.

12. The method of claim 7, further comprising sending, by the first processor, a number of lines to wait before resuming operation to the second processor.

13. A system, comprising:

a memory;

a first processor coupled to the memory;

a second processor coupled to the first processor via an interface, wherein the interface includes a primary link and a auxiliary link;

a display coupled to the second processor;

wherein the first processor is configured to;

in response to a determination that operation of the primary link has been terminated;

pre-charge the auxiliary link to a particular voltage level;

send a signal to resume operation to the second processor, the signal including a preamble followed by a link clock frequency change command, wherein the preamble includes a number of consecutive logic values; and

send at least one clock recovery parameter to the second processor.

14. The system of claim 13, wherein the at least one clock recovery parameter includes a number of clock recovery symbols to perform clock data recovery.

15. The system of claim 13, wherein the first processor is further configured to send the at least one clock recovery parameter via the primary link.

16. The system of claim 13, wherein the first processor is further configured to send the signal to resume operation via the auxiliary link.

17. The system of claim 13, wherein the first processor is further configured to send, to the second processor, a number of symbols to use in training the primary link.

18. The system of claim 17, wherein the first processor is further configured to send a number of lines to wait before resuming operation to the second processor.