Engine architecture for processing finite automata
First Claim
1. A security appliance operatively coupled to a network, the security appliance comprising:
- at least one Central Processing Unit (CPU) core; and
at least one hyper non-deterministic automata (HNA) processor operatively coupled to the at least one CPU core and specialized for non-deterministic finite automata (NFA) processing, the at least one HNA processor including;
a plurality of super-clusters, each super-cluster including a plurality of clusters, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs), the at least one CPU core configured to select at least one super-cluster of the plurality of super-clusters;
an HNA on-chip instruction queue configured to store at least one HNA instruction; and
an HNA scheduler configured to select a given HPU of the plurality of HPUs of the plurality of clusters of the at least one super-cluster selected and assign the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from the network.
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Abstract
An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.
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Citations
45 Claims
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1. A security appliance operatively coupled to a network, the security appliance comprising:
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at least one Central Processing Unit (CPU) core; and at least one hyper non-deterministic automata (HNA) processor operatively coupled to the at least one CPU core and specialized for non-deterministic finite automata (NFA) processing, the at least one HNA processor including; a plurality of super-clusters, each super-cluster including a plurality of clusters, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs), the at least one CPU core configured to select at least one super-cluster of the plurality of super-clusters; an HNA on-chip instruction queue configured to store at least one HNA instruction; and an HNA scheduler configured to select a given HPU of the plurality of HPUs of the plurality of clusters of the at least one super-cluster selected and assign the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from the network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A hyper non-deterministic finite automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing, the HNA processor comprising:
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a plurality of super-clusters, each super-cluster including a plurality of clusters, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs); and an HNA on-chip instruction queue configured to store at least one HNA instruction, the plurality of HPUs of the plurality of clusters of at least one selected super-cluster of the plurality of super-clusters forming a resource pool of HPUs available for assignment of the at least one HNA instruction; and an HNA scheduler configured to select a given HPU of the resource pool formed and assign the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from a network.
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24. A method comprising:
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operatively coupling at least one hyper non-deterministic automata (HNA) processor to at least one CPU core, the at least one HNA specialized for non-deterministic finite automata (NFA) processing; and configuring the at least one HNA processor to include; a plurality of super-clusters, each super-cluster including a plurality of clusters, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs), the at least one CPU core configured to select at least one super-cluster of the plurality of super-clusters; an HNA on-chip instruction queue configured to store at least one HNA instruction; and an HNA scheduler configured to select a given HPU of the plurality of HPUs of the plurality of clusters of the at least one super-cluster selected and assign the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from the network. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification