Memory controller that calibrates a transmit timing offset

• US 9,785,589 B2
• Filed: 07/29/2016
• Issued: 10/10/2017
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared LeVan, Donnelly, Kevin S., Sidiropoulos, Stefanos, Stark, Donald C., Horowitz, Mark A., Yu, Leung, Vu, Roxanne, Kim, Jun, Garlepp, Bruno W., Ho, Tsyr-Chyang, Lau, Benedict Chung-Kwong
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US15/222,987
• Publication Number:
  US 20170031854A1
• Time in Patent Office: 438 Days
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Claims

1. A memory controller to control a memory device, the memory controller comprising:

a transmitter to output a calibration sequence to the memory device;

a receiver to receive a signal representing a phase difference between a clock signal received at the memory device and the calibration sequence as received by the memory device; and

,

circuitry to apply a transmit timing offset to write data, based on the phase difference between the clock signal as received at the memory device and the calibration sequence as received by the memory device.

2. The memory controller of claim 1, wherein the calibration sequence is a data pattern sent by the memory controller.

3. The memory controller of claim 1, further comprising:

a transmit clock output to transmit the clock signal to the memory device, the clock signal to be based on a signal produced by a phase-locked loop (PLL) on the memory controller.

4. The memory controller of claim 1, further comprising:

a transmit clock output to transmit the clock signal to the memory device, the clock signal to be based on a signal produced by a delay-locked loop (DLL) on the memory controller.

5. The memory controller of claim 1, wherein the circuitry comprises a register to store a value representative of the transmit timing offset to apply to the write data.

6. The memory controller of claim 5, wherein the write data is output using the transmitter, and wherein the transmit timing offset is applied to the write data at the transmitter.

7. A memory controller to control a memory device, the memory controller comprising:

a first output to transmit, in response to a calibration mode, a calibration sequence to the memory device;

circuitry to place the memory device in a mode to receive the calibration sequence; and

,

a first input to receive, from the memory device, phase data representing a phase difference between a clock signal as received by the memory device and the calibration sequence as received by the memory device.

8. The memory controller of claim 7, wherein the calibration sequence is a data pattern sent by the memory controller via the first output.

9. The memory controller of claim 7, wherein the first output is associated with a data bus.

10. The memory controller of claim 7, further comprising a phase-locked loop (PLL) to produce the clock signal.

11. The memory controller of claim 7, further comprising a delay-locked loop (DLL) to produce the clock signal.

12. The memory controller of claim 7, further comprising:

a register to store a value representative of a timing offset to apply to data sent via the first output.

13. The memory controller of claim 12, wherein the value that is representative of the timing offset is based on the phase data representing the phase difference between the clock signal and the received calibration sequence.

14. The memory controller of claim 12, wherein the value is calculated from the phase data from the memory device.

15. A method of operating a memory controller, comprising:

sending, from the memory controller, a calibration sequence;

receiving, by the memory controller, a signal generated by the memory device that represents a phase difference between the calibration sequence, as received by the memory device, and a clock signal; and

,

adjusting, by the memory controller, a timing offset for write operations based on the phase difference between the calibration sequence, as received by the memory device, and the clock signal.

16. The method of claim 15, further including repeating the sending, receiving, and adjusting for each memory device of a plurality of memory devices, wherein the timing offsets for each memory device of the plurality of memory devices are independent of one another.

17. The method of claim 15, wherein the calibration sequence is a data pattern.

18. The method of claim 15, wherein the clock signal is generated by a phase-locked loop (PLL) on the memory controller.

19. The method of claim 15, wherein the clock signal is generated by a delay-locked loop (DLL) on the memory controller.

20. The method of claim 15, further comprising:

after the calibration sequence is complete, storing the timing offset for write operations.

21. The method of claim 16, further comprising:

after repeating the sending, receiving, and adjusting for each of a plurality of memory devices in the memory system, storing timing offsets for each of the plurality of memory devices in the memory system.