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Parallel incremental global routing

  • US 9,785,735 B1
  • Filed: 10/11/2016
  • Issued: 10/10/2017
  • Est. Priority Date: 10/11/2016
  • Status: Expired due to Fees
First Claim
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1. A computer-implemented method of performing global routing during integrated circuit fabrication, the method comprising:

  • performing a design change in a portion of an integrated circuit design as a thread using a processor, wherein each of two or more of the threads operates on a respective one of the portions of the integrated circuit design;

    determining using the processor, whether the design change requires rerouting;

    requesting, using the processor, a global routing lock based on the determining indicating that the design change requires the rerouting, wherein the global routing lock maintains a network list for every portion of the integrated circuit design as static;

    providing, using a router, control of the global routing lock to one of the two or more of the threads that request the global routing lock;

    performing, using the router, global routing for all of the two or more of the threads in parallel during the control of the global routing lock by the one of the two or more of the threads and updating the network list based on the global routing for all of the two or more of the threads with consideration of all modifications of the network list for all of the two or more of the threads; and

    fabricating a physical implementation of the integrated circuit design based on the global routing.

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