Driving circuit for non-volatile memory

• US 9,786,340 B2
• Filed: 11/09/2016
• Issued: 10/10/2017
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Po, Chen-Hao
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US15/347,158
• Publication Number:
  US 20170206941A1
• Time in Patent Office: 335 Days
• Field of Search: 36518523, 36518911, 36523006, 36518529, 36518909, 365145, 365149, 365154, 36518526, 36518528, 36518533, 36518905, 36518916, 365191, 365218, 365226, 365227, 365228
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.

Claims

1. A driving circuit connected to a memory array of a non-volatile memory, the driving circuit comprising a driving stage, the driving stage comprising:

a first level shifter comprising a first input terminal, a first inverted input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives a first control signal, and the first inverted input terminal receives an inverted first control signal; and

a second level shifter comprising a second input terminal, a second inverted input terminal, a third output terminal and a fourth output terminal, wherein the second input terminal receives a second control signal, the second inverted input terminal receives an inverted second control signal, the first output terminal and the third output terminal are directly connected with each other to generate an output signal, and the second output terminal and the fourth output terminal are directly connected with each other to generate an inverted output signal,

wherein the first level shifter is enabled according to an enabling signal set when the driving circuit is in a first operation mode, and the second level shifter is enabled according to the enabling signal set when the driving circuit is in a second operation mode.

2. The driving circuit as claimed in claim 1, wherein the first level shifter is a first cross couple latch, and the second level shifter is a second cross couple latch.

3. The driving circuit as claimed in claim 1, wherein the driving circuit further comprises a control stage, and the control stage comprises:

a first control circuit receiving a first input signal and an inverted first input signal, and converting the first input signal and the inverted first input signal into the first control signal and the inverted first control signal;

a second control circuit receiving a second input signal and an inverted second input signal, and converting the second input signal and the inverted second input signal into the second control signal and the inverted second control signal; and

an enabling circuit receiving the first input signal, the inverted first input signal, the second input signal and the inverted second input signal, and generating the enabling signal set, wherein the first level shifter or the second level shifter is disabled according to the enabling signal set.

4. The driving circuit as claimed in claim 3, wherein the first control circuit and the second control circuit receive a first supply voltage, so that the first control signal, the inverted first control signal, the second control signal and the inverted second control signal have voltage levels in a range between the first supply voltage and a ground voltage.

5. The driving circuit as claimed in claim 1, wherein the enabling signal set contains a first enabling signal, a second enabling signal, a third enabling signal, an inverted third enabling signal and a fourth enabling signal, wherein the second level shifter comprises:

a first p-type transistor, wherein a source terminal of the first p-type transistor is connected with a second supply voltage, and a gate terminal of the first p-type transistor is connected with a node y1;

a second p-type transistor, wherein a source terminal of the second p-type transistor is connected with the second supply voltage, and a gate terminal of the second p-type transistor is connected with a node y2;

a third p-type transistor, wherein a source terminal of the third p-type transistor is connected with a drain terminal of the first p-type transistor, a gate terminal of the third p-type transistor receives the second enabling signal, and a drain terminal of the third p-type transistor is connected with the node y2;

a fourth p-type transistor, wherein a drain terminal of the fourth p-type transistor is connected with a drain terminal of the second p-type transistor, a gate terminal of the fourth p-type transistor receives the second enabling signal, and a drain terminal of the fourth p-type transistor is connected with the node y1;

a fifth p-type transistor, wherein a source terminal of the fifth p-type transistor is connected with the node y2, a gate terminal of the fifth p-type transistor receives the fourth enabling signal;

a sixth p-type transistor, wherein a source terminal of the sixth p-type transistor is connected with the node y1, and a gate terminal of the sixth p-type transistor receives the fourth enabling signal;

a seventh p-type transistor, wherein a source terminal of the seventh p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the seventh p-type transistor are connected with the node y2;

an eighth p-type transistor, wherein a source terminal of the eighth p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the eighth p-type transistor are connected with the node y1;

a first n-type transistor, wherein a source terminal of the first n-type transistor is connected with a third supply voltage, and a gate terminal of the first n-type transistor receives the second control signal;

a second n-type transistor, wherein a source terminal of the second n-type transistor is connected with the third supply voltage, and a gate terminal of the second n-type transistor receives the inverted second control signal;

a third n-type transistor, wherein a source terminal of the third n-type transistor is connected with a drain terminal of the first n-type transistor, a gate terminal of the third n-type transistor receives the third enabling signal, and a drain terminal of the third n-type transistor is connected with a drain terminal of the fifth p-type transistor; and

a fourth n-type transistor, wherein a source terminal of the fourth n-type transistor is connected with a drain terminal of the second n-type transistor, a gate terminal of the fourth n-type transistor receives the third enabling signal, and a drain terminal of the fourth n-type transistor is connected with a drain terminal of the sixth p-type transistor.

6. The driving circuit as claimed in claim 5, wherein the first level shifter comprises:

a ninth p-type transistor, wherein a source terminal of the ninth p-type transistor is connected with the second supply voltage, and a gate terminal of the ninth p-type transistor is connected with a node x1;

a tenth p-type transistor, wherein a source terminal of the tenth p-type transistor is connected with the second supply voltage, and a gate terminal of the tenth p-type transistor is connected with a node x2;

an eleventh p-type transistor, wherein a source terminal of the eleventh p-type transistor is connected with a drain terminal of the ninth p-type transistor, a gate terminal of the eleventh p-type transistor receives the first enabling signal, and a drain terminal of the eleventh p-type transistor is connected with the node x2;

a twelfth p-type transistor, wherein a source terminal of the twelfth p-type transistor is connected with a drain terminal of the tenth p-type transistor, a gate terminal of the twelfth p-type transistor receives the first enabling signal, and a drain terminal of the twelfth p-type transistor is connected with the node x1;

a thirteenth p-type transistor, wherein a source terminal of the thirteenth p-type transistor is connected with the node x2, a gate terminal of the thirteenth p-type transistor receives the fourth enabling signal;

a fourteenth p-type transistor, wherein a source terminal of the fourteenth p-type transistor is connected with the node x1, and a gate terminal of the fourteenth p-type transistor receives the fourth enabling signal;

a fifteenth p-type transistor, wherein a source terminal of the fifteenth p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the fifteenth p-type transistor are connected with the node x2;

a sixteenth p-type transistor, wherein a source terminal of the sixteenth p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the sixteenth p-type transistor are connected with the node x1;

a fifth n-type transistor, wherein a source terminal of the fifth n-type transistor is connected with the third supply voltage, and a gate terminal of the fifth n-type transistor receives the first control signal;

a sixth n-type transistor, wherein a source terminal of the sixth n-type transistor is connected with the third supply voltage, and a gate terminal of the sixth n-type transistor receives the inverted first control signal;

a seventh n-type transistor, wherein a source terminal of the seventh n-type transistor is connected with a drain terminal of the fifth n-type transistor, a gate terminal of the seventh n-type transistor receives the third enabling signal, and a drain terminal of the seventh n-type transistor is connected with a drain terminal of the thirteenth p-type transistor; and

an eighth n-type transistor, wherein a source terminal of the eighth n-type transistor is connected with a drain terminal of the sixth n-type transistor, a gate terminal of the eighth n-type transistor receives the third enabling signal, and a drain terminal of the eighth n-type transistor is connected with a drain terminal of the fourteenth p-type transistor,

wherein the node x1 and the node y1 are directly connected with each other to generate the output signal, and the node x2 and the node y2 are directly connected with each other to generate the inverted output signal.

7. The driving circuit as claimed in claim 6, wherein a first size ratio between the p-type transistor and the n-type transistor of the first level shifter is larger than a second size ratio between the p-type transistor and the n-type transistor of the second level shifter.

8. The driving circuit as claimed in claim 6, wherein when the driving circuit is in the first operation mode, the first supply voltage has a first voltage value, the second supply voltage is equal to the first voltage value, and the third supply voltage is equal to the ground voltage, wherein when the driving circuit is in the second operation mode, the first supply voltage has a second voltage value, the second supply voltage is equal to N times of the second voltage value, and the third supply voltage is equal the ground voltage.

9. The driving circuit as claimed in claim 6, wherein first level shifter further comprises:

a first pull-down circuit connected between the node x2 and the third supply voltage; and

a second pull-down circuit connected between the node x1 and the third supply voltage;

wherein the first pull-down circuit is activated and the second pull-down circuit is inactived when the output signal is equal to the second supply voltage and the inverted output signal is equal to the third supply voltage, and the first pull-down circuit is inactivated and the second pull-down circuit is actived when the output signal is the third supply voltage and the inverted output signal is the second supply voltage.

10. The driving circuit as claimed in claim 9, wherein first pull-down circuit comprises:

a ninth n-type transistor having a drain terminal connected with the node x2 and a gate terminal connected with the third enabling signal; and

a tenth n-type transistor having a drain terminal connected with a source terminal of the ninth n-type transistor, a gate terminal connected with the first control signal and a source terminal connected with the third supply voltage; and

wherein second pull-down circuit comprises;

a eleventh n-type transistor having a drain terminal connected with the node x1 and a gate terminal connected with the third enabling signal; and

a twelfth n-type transistor having a drain terminal connected with a source terminal of the eleventh n-type transistor, a gate terminal connected with the inverted first control signal and a source terminal connected with the third supply voltage.

11. The driving circuit as claimed in claim 5, wherein the first level shifter comprises:

a ninth p-type transistor, wherein a source terminal of the ninth p-type transistor is connected with the second supply voltage, and a gate terminal of the ninth p-type transistor is connected with a node z1;

a tenth p-type transistor, wherein a source terminal of the tenth p-type transistor is connected with the second supply voltage, and a gate terminal of the tenth p-type transistor is connected with a node z2;

an eleventh p-type transistor, wherein a source terminal of the eleventh p-type transistor is connected with a drain terminal of the ninth p-type transistor, a gate terminal of the eleventh p-type transistor receives the first enabling signal, and a drain terminal of the eleventh p-type transistor is connected with the node z2;

a twelfth p-type transistor, wherein a source terminal of the twelfth p-type transistor is connected with a drain terminal of the tenth p-type transistor, a gate terminal of the twelfth p-type transistor receives the first enabling signal, and a drain terminal of the twelfth p-type transistor is connected with the node z1;

a thirteen p-type transistor, wherein a source terminal of the thirteenth p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the thirteenth p-type transistor are connected with the node z2;

a fourteenth p-type transistor, wherein a source terminal of the fourteenth p-type transistor receives the inverted third enabling signal, and a gate terminal and a drain terminal of the fourteenth p-type transistor are connected with the node z1;

a fifth n-type transistor, wherein a source terminal of the fifth n-type transistor is connected with the third supply voltage, and a gate terminal of the fifth n-type transistor receives the first control signal;

a sixth n-type transistor, wherein a source terminal of the sixth n-type transistor is connected with the third supply voltage, and a gate terminal of the sixth n-type transistor receives the inverted first control signal;

a seventh n-type transistor, wherein a source terminal of the seventh n-type transistor is connected with a drain terminal of the fifth n-type transistor, a gate terminal of the seventh n-type transistor receives the third enabling signal, and a drain terminal of the seventh n-type transistor is connected with the node z2; and

an eighth n-type transistor, wherein a source terminal of the eighth n-type transistor is connected with a drain terminal of the sixth n-type transistor, a gate terminal of the eighth n-type transistor receives the third enabling signal, and a drain terminal of the eighth n-type transistor is connected with the node z1,

wherein the node z1 and the node y1 are directly connected with each other to generate the output signal, and the node z2 and the node y2 are directly connected with each other to generate the inverted output signal.

12. The driving circuit as claimed in claim 11, wherein a first size ratio between the p-type transistor and the n-type transistor of the first level shifter is larger than a second size ratio between the p-type transistor and the n-type transistor of the second level shifter.

13. The driving circuit as claimed in claim 11, wherein when the driving circuit is in the first operation mode, the first supply voltage has a first voltage value, the second supply voltage is equal to the first voltage value, and the third supply voltage is equal to the ground voltage, wherein when the driving circuit is in the second operation mode, the first supply voltage has a second voltage value, the second supply voltage is equal to N times of the second voltage value, and the third supply voltage is equal to the ground voltage.

14. The driving circuit as claimed in claim 11, wherein first level shifter further comprises:

a first pull-down circuit connected between the node z2 and the third supply voltage; and

a second pull-down circuit connected between the node z1 and the third supply voltage;

wherein the first pull-down circuit is activated and the second pull-down circuit is inactived when the output signal is equal to the second supply voltage and the inverted output signal is equal to the third supply voltage, and the first pull-down circuit is inactivated and the second pull-down circuit is actived when the output signal is the third supply voltage and the inverted output signal is the second supply voltage.

15. The driving circuit as claimed in claim 14, wherein first pull-down circuit comprises:

a ninth n-type transistor having a drain terminal connected with the node z2 and a gate terminal connected with the third enabling signal; and

a tenth n-type transistor having a drain terminal connected with a source terminal of the ninth n-type transistor, a gate terminal connected with the first control signal and a source terminal connected with the third supply voltage; and

wherein second pull-down circuit comprises;

a eleventh n-type transistor having a drain terminal connected with the node z1 and a gate terminal connected with the third enabling signal; and

a twelfth n-type transistor having a drain terminal connected with a source terminal of the eleventh n-type transistor, a gate terminal connected with the inverted first control signal and a source terminal connected with the third supply voltage.

16. The driving circuit as claimed in claim 5, wherein the first level shifter comprises:

a ninth p-type transistor, wherein a source terminal of the ninth p-type transistor is connected with the second supply voltage, and a gate terminal of the ninth p-type transistor is connected with a node w1;

a tenth p-type transistor, wherein a source terminal of the tenth p-type transistor is connected with the second supply voltage, and a gate terminal of the tenth p-type transistor is connected with a node w2;

an eleventh p-type transistor, wherein a source terminal of the eleventh receives the inverted third enabling signal, and a gate terminal and a drain terminal of the eleventh p-type transistor are connected with a node w2;

a twelfth p-type transistor, wherein a source terminal of the twelfth receives the inverted third enabling signal, and a gate terminal and a drain terminal of the twelfth p-type transistor are connected with a node w1;

a fifth n-type transistor, wherein a source terminal of the fifth n-type transistor is connected with a third supply voltage, and a gate terminal of the fifth n-type transistor receives the first control signal;

a sixth n-type transistor, wherein a source terminal of the sixth n-type transistor is connected with the third supply voltage, and a gate terminal of the sixth n-type transistor receives the inverted first control signal;

a seventh n-type transistor, wherein a source terminal of the seventh n-type transistor is connected with a drain terminal of the fifth n-type transistor, a gate terminal of the seventh n-type transistor receives the third enabling signal, and a drain terminal of the seventh n-type transistor is connected with the node w2; and

an eighth n-type transistor, wherein a source terminal of the eighth n-type transistor is connected with a drain terminal of the sixth n-type transistor, a gate terminal of the eighth n-type transistor receives the third enabling signal, and a drain terminal of the eighth n-type transistor is connected with the node w1,

wherein the node w1 and the node y1 are directly connected with each other to generate the output signal, and the node w2 and the node y2 are directly connected with each other to generate the inverted output signal.

17. The driving circuit as claimed in claim 16, wherein a first size ratio between the p-type transistor and the n-type transistor of the first level shifter is larger than a second size ratio between the p-type transistor and the n-type transistor of the second level shifter.

18. The driving circuit as claimed in claim 16, wherein when the driving circuit is in the first operation mode, the first supply voltage has a first voltage value, the second supply voltage is equal to the first voltage value, and the third supply voltage is equal to the ground voltage, wherein when the driving circuit is in the second operation mode, the first supply voltage has a second voltage value, the second supply voltage is equal to N times of the second voltage value, the third supply voltage is equal to the ground voltage, and the fourth supply voltage is equal to M times of the second voltage value, wherein N is larger than M.

19. The driving circuit as claimed in claim 16, wherein first level shifter further comprises:

a first pull-down circuit connected between the node w2 and the third supply voltage; and

a second pull-down circuit connected between the node w1 and the third supply voltage;

wherein the first pull-down circuit is activated and the second pull-down circuit is inactived when the output signal is equal to the second supply voltage and the inverted output signal is equal to the third supply voltage, and the first pull-down circuit is inactivated and the second pull-down circuit is actived when the output signal is the third supply voltage and the inverted output signal is the second supply voltage.

20. The driving circuit as claimed in claim 19, wherein first pull-down circuit comprises:

a ninth n-type transistor having a drain terminal connected with the node w2 and a gate terminal connected with the third enabling signal; and

a tenth n-type transistor having a drain terminal connected with a source terminal of the ninth n-type transistor, a gate terminal connected with the first control signal and a source terminal connected with the third supply voltage; and

wherein second pull-down circuit comprises;

a eleventh n-type transistor having a drain terminal connected with the node w1 and a gate terminal connected with the third enabling signal; and

a twelfth n-type transistor having a drain terminal connected with a source terminal of the eleventh n-type transistor, a gate terminal connected with the inverted first control signal and a source terminal connected with the third supply voltage.