Static random access memory (SRAM) tracking cells and methods of forming same

• US 9,786,359 B2
• Filed: 05/02/2016
• Issued: 10/10/2017
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US15/144,346
• Publication Number:
  US 20170221552A1
• Time in Patent Office: 526 Days
• Field of Search: 365154, 365203, 365194, 365226, 365148, 365156, 36518906, 365191, 365211, 36523006, 365 51, 365130, 365163, 365189011
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G

Abstract

An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.

Claims

1. A static random access memory (SRAM) array comprising:

a writable SRAM cell disposed in a first row of the SRAM array; and

an SRAM read current tracking cell in the first row of the SRAM array, wherein the SRAM current tracking cell comprises;

a first read pull-down transistor comprising;

a first gate electrically connected to a first positive supply voltage line without any intervening active devices, and wherein a voltage applied to the first gate is directly tied to a voltage of the first positive supply voltage line;

a first source/drain electrically connected to a first ground line; and

a second source/drain; and

a first read pass-gate transistor comprising;

a third source/drain electrically connected to the second source/drain; and

a fourth source/drain electrically connected to a read tracking bit line (BL), wherein the read tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit.

2. The SRAM array of claim 1 further comprising a first SRAM tracking read pass-gate control cell in the first row of the SRAM array and adjacent the SRAM tracking read current tracking cell, wherein the first SRAM tracking read pass-gate control cell is disposed on an opposing side of the SRAM read current tracking cell as the writable SRAM cell, and wherein the first SRAM tracking read pass-gate control cell is configured to electrically connect a second gate of the first read pass-gate transistor to positive supply voltage.

3. The SRAM array of claim 2, wherein the second gate of the first read pass-gate transistor extends into the first SRAM tracking read pass-gate control cell.

4. The SRAM array of claim 1 further comprising an SRAM read capacitance tracking cell in a second row of the SRAM array and comprising:

a second read pull-down transistor comprising;

a third gate electrically connected to the first ground line;

a fifth source/drain electrically connected to a second ground line; and

a sixth source/drain; and

a second read pass-gate transistor comprising;

a seventh source/drain connected to the second source/drain; and

an eighth source/drain connected to the read tracking BL.

5. The SRAM array of claim 4 further comprising a second SRAM tracking read pass-gate control cell in the second row of the SRAM array and adjacent the SRAM read capacitance tracking cell, wherein the second SRAM tracking read pass-gate control cell electrically connects a fourth gate of the second read pass-gate transistor to a third ground line extending through the second SRAM tracking read pass-gate control cell.

6. The SRAM array of claim 1, wherein the SRAM read current tracking cell comprises a pair of cross-coupled inverters, and wherein the first read pull-down transistor shares a gate electrode with one of the pair of cross-coupled inverters.

7. The SRAM array of claim 1, wherein the SRAM read current tracking cell comprises a write pass-gate transistor comprising:

a fourth gate electrically connected to a fourth ground line; and

a ninth source/drain electrically connected to a dummy bit line.

8. A static random access memory (SRAM) tracking cell comprising:

a first gate electrode disposed over a first active region of a first invertor;

a second gate electrode; and

a second active region under the first gate electrode and the second gate electrode, wherein the second active region provides;

a first source/drain region electrically connected to a ground line; and

a second source/drain region on an opposite side of the first gate electrode as the first source/drain region, wherein the second source/drain region is further disposed between the first gate electrode and the second gate electrode; and

a third source/drain region electrically connected to a tracking bit line (BL), wherein the tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit.

9. The SRAM tracking cell of claim 8, wherein the first gate electrode is electrical connected to a positive voltage power supply line by a source/drain contact of a second invertor cross-coupled with the first invertor.

10. The SRAM tracking cell of claim 8, wherein the first gate electrode is electrically connected to a ground line.

11. The SRAM tracking cell of claim 8, wherein the second gate electrode extends into an SRAM tracking read pass-gate control cell, and wherein the SRAM tracking read pass-gate control cell electrically connects the second gate electrode to a read current tracking control circuit.

12. The SRAM tracking cell of claim 8, wherein the second gate electrode extends into an SRAM tracking read pass-gate control cell, and wherein the SRAM tracking read pass-gate control cell electrically connects the second gate electrode to a ground line extending through the SRAM tracking read pass-gate control cell.

13. The SRAM tracking cell of claim 8 further comprising a third gate electrode adjacent the second gate electrode and over the first active region, wherein the third gate electrode is electrically connected to ground.

14. The SRAM tracking cell of claim 8 further comprising a third gate electrode adjacent the second gate electrode and over the first active region, wherein the first active region provides a fourth source/drain region adjacent the third gate electrode, wherein the fourth source/drain region is electrically connected to a write tracking BL, and wherein the writing tracking BL is electrically connected to a write SA timing control circuit.

15. A method comprising:

disposing a static random access memory (SRAM) read current tracking cell in a same row of an SRAM array as a writable SRAM cell, wherein the SRAM read current tracking cell comprises;

a first invertor comprising a first gate;

a first read pull-down transistor comprising a second gate, a first source/drain, and a second source/drain; and

a first read pass-gate transistor comprising a third gate, a third source/drain electrically connected to the second source/drain, and a fourth source/drain;

electrically connecting the second gate to a positive power voltage supply line through a gate contact of the first gate, wherein a voltage applied to the second gate is directly tied to a voltage of the positive power voltage supply line;

electrically connecting the first source/drain to a ground line;

electrically connecting the third gate to a read current tracking control circuit;

electrically connecting the fourth source/drain to a tracking bit line (BL); and

electrically connecting the tracking BL to a read sense amplifier (SA) timing control circuit.

16. The method of claim 15, wherein the read SA timing control circuit is configured to:

determine a discharge time of the tracking BL, wherein the discharge time is an amount of time taken, by the tracking BL, to discharge from positive supply voltage to ground through the first read pass-gate transistor and the first read pull-down transistor; and

adjust a clock cycle of a read SA in accordance the discharge time of the read tracking BL.

17. The method of claim 16 further comprising charging the tracking BL to positive supply voltage, wherein the read current tracking control circuit is configured to apply the positive supply voltage to the third gate after the tracking BL is charged.

18. The method of claim 16, wherein the read SA is electrically connected to a read bit line (RBL) extending through the writable SRAM cell.

19. The method of claim 15 further comprising:

electrically connecting the tracking BL to a fifth source/drain of a second read pull-down transistor; and

electrically connecting a third gate of the second read pull-down transistor to a ground line.

20. The method of claim 15, wherein the positive power supply voltage line and the ground line are substantially parallel and are disposed in a same conductive line layer.