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Static random access memory (SRAM) tracking cells and methods of forming same

  • US 9,786,359 B2
  • Filed: 05/02/2016
  • Issued: 10/10/2017
  • Est. Priority Date: 01/29/2016
  • Status: Active Grant
First Claim
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1. A static random access memory (SRAM) array comprising:

  • a writable SRAM cell disposed in a first row of the SRAM array; and

    an SRAM read current tracking cell in the first row of the SRAM array, wherein the SRAM current tracking cell comprises;

    a first read pull-down transistor comprising;

    a first gate electrically connected to a first positive supply voltage line without any intervening active devices, and wherein a voltage applied to the first gate is directly tied to a voltage of the first positive supply voltage line;

    a first source/drain electrically connected to a first ground line; and

    a second source/drain; and

    a first read pass-gate transistor comprising;

    a third source/drain electrically connected to the second source/drain; and

    a fourth source/drain electrically connected to a read tracking bit line (BL), wherein the read tracking BL is electrically connected to a read sense amplifier (SA) timing control circuit.

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