Detecting and managing bad columns

• US 9,786,388 B1
• Filed: 10/09/2013
• Issued: 10/10/2017
• Est. Priority Date: 10/09/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Nassie, Amir
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/050,249
• Time in Patent Office: 1,462 Days
• Field of Search: 714718, 714719, 714723, 714773, 714704, 714 48, 365200, 365201, 36518533, 36518509, 36518522, 711103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/804 to prevent clustered faults
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A system, computer readable medium and a method. The method may include sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write input data to the NAND flash memory array to provide programmed data; reading from the NAND flash memory array the programmed data to provide read data; comparing the input data and the read data to provide column errors statistics at a column resolution; and defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics.

Claims

1. A method for detecting bad columns of a NAND flash memory array, comprising:

sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write the input data to the NAND flash memory array to provide programmed data;

reading from the NAND flash memory array the programmed data to provide read data;

comparing the input data and the read data to provide column error statistics that is indicative of a number of errors per column;

wherein the NAND flash memory array comprises multi-level flash memory cells and is configured to store different types of pages that include a most significant bit (MSB) page that is programmed using MSB programming and a least significant bit (LSB) page that is programmed using LSB programming;

wherein the column error statistics comprises column error statistics for each page in the different types of pages; and

defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics.

2. The method according to claim 1, wherein the defining of the bad columns comprises defining a column of the NAND flash memory array as a bad column if a number of errors associated with the column exceeds an error threshold.

3. The method according to claim 1, wherein the method comprises assigning a reliability score per each column in response to a number of errors associated with the column;

wherein the NAND flash memory array is an erase block that has a given number of pages;

wherein the reliability score of each column comprises a logarithm of a ratio between a number of errors in the column and the given number of pages minus the number of errors in the column.

4. The method according to claim 1, comprising defining an encoding scheme for data units to be written to the NAND flash memory array while constraining a value of bits to be written to the bad columns to be of an erase value.

5. The method according to claim 1, comprising:

receiving, by the flash memory controller, an input data unit to be written to the NAND flash memory array;

generating, by the flash memory controller, an updated data unit by adding dummy bits to the input data unit at locations of the updated data unit that are going to be written to any of the bad columns of the NAND flash memory array; and

sending the updated data unit to the NAND flash memory unit and instructing the NAND flash memory unit to write the updated data unit to the NAND flash memory array.

6. The method according to claim 5, wherein a value of a dummy bit to be written, instead a data bit, to a flash memory cell of a bad column equals a value of the data bit.

7. The method according to claim 1, comprising defining a mapping of bits of codewords to flash memory cells of the NAND flash memory unit in response to locations of the bad columns.

8. The method according to claim 7, wherein the defining of the mapping reduces an effect of an uneven distribution of bad columns within NAND flash memory unit portions allocated for storing the codewords.

9. The method according to claim 7, wherein a mapping of bits of a codeword of the codewords, is further responsive to a relationship between (a) a size of a NAND flash memory unit portion allocated for storing the codeword, and (b) a sum of (i) a size of the codeword and (ii) a number of flash memory cells that belong to a bad column within the NAND flash memory unit portion allocated for storing the codeword.

10. The method according to claim 1, comprising swapping bits that belong to different codewords in response to an amount of bad columns and to a location of bad columns in NAND flash memory units portions initially allocated for storing the different codewords.

11. A method for detecting bad columns of a NAND flash memory array, comprising:

sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write the input data to the NAND flash memory array to provide programmed data;

reading from the NAND flash memory array the programmed data to provide read data;

comparing the input data and the read data to provide column error statistics that is indicative of a number of errors per column;

defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics;

determining an encoding parameter in response to the column error statistics; and

assigning a reliability score per each column in response to a number of errors associated with the column, wherein the reliability score of each column comprises a logarithm of a ratio between a number of errors in the column and the given number of pages minus the number of errors in the column.

12. The method according to claim 11 wherein the encoding parameter is a bit error rate of a code to be used for providing codewords.

13. The method according to claim 11 wherein the encoding parameter is a number of redundancy bits to be allocated per codeword.

14. The method according to claim 13 wherein the number of redundancy bits is determined to optimize a value of a function of (a) bad column distribution between different dies of the NAND flash memory unit and (b) a bit error rate function.

15. The method according to claim 11 wherein the determining is responsive to column error statistics of different dies of NAND flash memory unit that are activated at a certain point in time.

16. The method according to claim 11 wherein the encoding parameter is a bit error rate of a code to be used for providing codewords.

17. The method according to claim 11 wherein the flash memory array is spread over multiple dies of the flash memory unit.

18. A non-transitory computer readable medium that stores instructions to be executed by a computer and cause the computer to perform stages comprising:

instructing a NAND flash memory unit that comprises a NAND flash memory array to write input data to the NAND flash memory array to provide programmed data;

reading from the NAND flash memory array the programmed data to provide read data;

comparing the input data and the read data to provide column error statistics that is indicative of a number of errors per column;

wherein the NAND flash memory array comprises multi-level flash memory cells and is configured to store different types of pages that include a most significant bit (MSB) page that is programmed using MSB programming and a least significant bit (LSB) page that is programmed using LSB programming;

wherein the column error statistics comprises column error statistics for each page in the different types of pages; and

defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics.

19. A system, comprising a flash memory controller that comprises a control circuit and an interface;

wherein the interface is arranged to instruct a NAND flash memory unit that comprises a NAND flash memory array to write input data to the NAND flash memory array to provide programmed data;

wherein the interface is arranged to read from the NAND flash memory array the programmed data to provide read data;

wherein the control circuit is arranged to;

(a) compare the input data and the read data to provide column error statistics that is indicative of a number of errors per column;

wherein the NAND flash memory array comprises multi-level flash memory cells and is configured to store different types of pages that include a most significant bit (MSB) that is programmed using MSB programming page and a least significant bit (LSB) page that is programmed using LSB programming;

wherein the column error statistics comprises column error statistics for each page in the different types of pages; and

(b) define bad columns of the NAND flash memory array in response to the column error statistics.

20. The system of claim 19, wherein the control circuit assigns a reliability score per each column in response to a number of errors associated with the column, wherein the NAND flash memory array is an erase block that has a given number of pages, and wherein the reliability score of each column comprises a logarithm of a ratio between a number of errors in the column and the given number of pages minus the number of errors in the column.