Elongated bump structures in package structure

• US 9,786,621 B2
• Filed: 10/07/2015
• Issued: 10/10/2017
• Est. Priority Date: 01/07/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Chita, Chen, Chen-Shien, Tseng, Ming Hung, Chuang, Yao-Chun
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Gray, Aaron
• Application Number:
  US14/877,525
• Publication Number:
  US 20160027752A1
• Time in Patent Office: 734 Days
• Field of Search: 257737, 257773, 257692, 257E23021, 438613
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/14155 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81024 : Applying flux to the bonding area
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81464 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/81484 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

Claims

1. A package structure, comprising:

a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a first length measured along a long axis of the conductive pillar and a first width measured along a short axis of the conductive pillar, wherein the first length is different from the first width; and

a substrate comprising a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a first portion of the pad region, wherein a center of a top surface of the conductive pillar overlaps with a center of the first portion of the pad region in a top view, wherein the chip is attached to the pad region of the substrate, wherein the opening has a first dimension measured along the long axis and a second dimension measured along the short axis, and wherein the first length is greater than the first dimension by at least 20 μ

m and the first width is less than the second dimension, wherein the bump structure further comprises an under bump metallurgy layer, and wherein the conductive pillar is disposed between the under bump metallurgy layer and the substrate.

2. The package structure of claim 1, further comprising a solder joint region between the conductive pillar and the pad region, wherein the solder joint extends into the opening.

3. The package structure of claim 1, wherein the mask layer is formed of a solder resist material layer.

4. The package structure of claim 1, wherein the conductive pillar comprises copper or copper alloy.

5. The package structure of claim 1, wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.

6. The package structure of claim 1, wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.

7. The package structure of claim 1, wherein the pad region further comprises:

a via portion extending through the opening and disposed over the first portion; and

a second portion over the via portion and the mask layer.

8. The package structure of claim 1, wherein the first dimension is substantially equal to the second dimension.

9. The package structure of claim 1, wherein the width is less than the second dimension by at least 2 μ

m.

10. A package structure, comprising:

a chip comprising;

an under bump metallurgy layer; and

a conductive pillar over the under bump metallurgy layer and having a length measured along a first axis of the conductive pillar and a width measured along a second axis of the conductive pillar, wherein the length is greater than the width and wherein the first axis and the second axis are substantially perpendicular; and

a substrate comprising a mask layer and a conductive pad, wherein the conductive pillar is bonded to the conductive pad by a solder ball, wherein an opening in the mask layer is disposed over at least a portion of the conductive pad, wherein the conductive pillar extends past edges of the opening along the first axis, and wherein the opening extends past edges of the conductive pillar along the second axis by at least 2 μ

m.

11. The package structure of claim 10, wherein the conductive pad comprises:

a bottom portion under the opening;

a via portion extending through the opening; and

a top portion extending over the opening.

12. The package structure of claim 10, wherein the mask layer is formed of a solder resist material layer.

13. The package structure of claim 10, wherein the conductive pillar comprises copper or copper alloy.

14. The package structure of claim 10, wherein the solder ball extends through the opening.

15. The package structure of claim 10, wherein the conductive pillar extends past edges of the opening along the first axis by at least 20 μ

m.

16. A method of forming a package structure, comprising:

forming a bump structure on a semiconductor substrate, wherein the bump structure comprises;

an under bump metallurgy layer; and

a conductive pillar over the under bump metallurgy layer, wherein the conductive pillar comprises a length measured along a long axis of the conductive pillar and a width measured along a short axis of the conductive pillar; and

bonding the semiconductor substrate to a package substrate by bonding the bump structure to a pad region of the package substrate, wherein the package substrate comprises;

a solder resist layer over at least a portion of the pad region; and

an opening in the solder resist layer exposing the portion of the pad region, wherein the opening has a first dimension measured along the long axis and a second dimension measured along the short axis, and wherein the length is greater than the first dimension by at least 20 μ

m and the width is less than the second dimension, wherein the opening has a first center aligned with a second center of the conductive structure.

17. The method of claim 16, further comprising:

prior to bonding the semiconductor substrate to the package substrate, forming a solder cap over the conductive pillar.

18. The method of claim 16, further comprising:

prior to bonding the semiconductor substrate to the package substrate, forming a solder layer a top surface and sidewalls of the pad region.

19. The method of claim 16, further comprising:

prior to bonding the semiconductor substrate to the package substrate, forming a solder layer in the opening and extending over the solder resist layer.

20. The method of claim 16, wherein the length is greater than the width, and wherein the first dimension is substantially equal to the second dimension.