Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
First Claim
1. A package structure, comprising:
- a photonics package comprising;
a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer;
an integrated optical waveguide structure patterned from the active silicon layer of the first integrated circuit chip;
an optoelectronics device mounted on the buried oxide layer of the first integrated circuit chip in alignment with at least a portion of the integrated optical waveguide structure;
an interposer bonded to the BEOL structure of the first integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and wiring to provide electrical connections to the BEOL structure;
a second integrated circuit chip;
a package interposer, wherein the photonics package is mounted to a first side of the package interposer and wherein the second integrated circuit chip is mounted to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and
an application board having an integrated recess formed in one side of the application board, wherein the package interposer is mounted to the application board with at least a portion of the photonics package disposed within the integrated recess of the application board;
wherein the application board comprises a plurality of thermal vias formed therein in alignment with the integrated recess, wherein photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias.
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Accused Products
Abstract
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
60 Citations
20 Claims
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1. A package structure, comprising:
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a photonics package comprising; a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer; an integrated optical waveguide structure patterned from the active silicon layer of the first integrated circuit chip; an optoelectronics device mounted on the buried oxide layer of the first integrated circuit chip in alignment with at least a portion of the integrated optical waveguide structure; an interposer bonded to the BEOL structure of the first integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and wiring to provide electrical connections to the BEOL structure; a second integrated circuit chip; a package interposer, wherein the photonics package is mounted to a first side of the package interposer and wherein the second integrated circuit chip is mounted to a second side of the package interposer, opposite the first side of the package interposer, wherein the package interposer comprises electrical wiring and through vias to provide electrical connections between the photonics package and the second integrated circuit chip; and an application board having an integrated recess formed in one side of the application board, wherein the package interposer is mounted to the application board with at least a portion of the photonics package disposed within the integrated recess of the application board; wherein the application board comprises a plurality of thermal vias formed therein in alignment with the integrated recess, wherein photonics package is disposed within the integrated recess such that a backside of the optoelectronics device of the photonics package is in thermal contact with the plurality of thermal vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A package structure, comprising:
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a photonics package comprising; a first integrated circuit chip comprising a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer; an integrated optical waveguide structure patterned from the active silicon layer of the first integrated circuit chip; an optoelectronics device mounted on the buried oxide layer of the first integrated circuit chip in alignment with at least a portion of the integrated optical waveguide structure; an interposer bonded to the BEOL structure of the first integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and wiring to provide electrical connections to the BEOL structure; a second integrated circuit chip; a package interposer having a hole formed through the package interposer; and an application board; wherein the second integrated circuit chip is flip-chip mounted to a first side of the package interposer; wherein the photonics package is mounted to a front side of the second integrated circuit chip and disposed within the hole of the package interposer; wherein a second side of the package interposer is mounted to a first side of the application board; wherein the application board comprises a heat sink formed on the first side of the application board, and a plurality of thermal vias formed therein in alignment with heat sink; wherein the photonics package is disposed within the hole of the package interposer such that a backside of the optoelectronics device of the photonics package is in thermal contact with the heat sink formed on the first side of the application board. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification