Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
First Claim
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1. A process for making a semiconductor wafer that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, and a gate contact (GATECNT) layer, the process comprising at least:
- (i) creating a first design of experiments (DOE) by instantiating, on the wafer, at least first and second non-contact electrical measurement (NCEM)-enabled fill cells in a standard cell form, with first and second supply rails that extend horizontally across the cells and uniformly spaced GATE stripes that extend vertically across the cells, said creating further including instantiating, on the wafer, test area patterning that comprises at least first and second features, arranged in a via open configuration, with the first feature electrically connected to an NCEM pad and the second feature electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area using a non-contact (NC) measurement at the NCEM pad, said creating further including providing at least one patterning difference between the first and second NCEM-enabled fill cells that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; and
,(ii) creating a second DOE by instantiating, on the wafer, at least first and second NCEM-enabled fill cells in a standard cell form, with first and second supply rails that extend horizontally across the cells and uniformly spaced GATE stripes that extend vertically across the cells, said creating further including instantiating, on the wafer, test area patterning that comprises at least first and second features, arranged in a stitch open configuration, with the first feature electrically connected to an NCEM pad and the second feature electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area using a NC measurement at the NCEM pad, said creating further including providing at least one patterning difference between the first and second NCEM-enabled fill cells that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell;
wherein creating the first and second DOEs further comprises instantiating all of the NCEM-enabled fill cells in the first and second DOEs in a compatible standard cell form, with identical spacing between the first and second supply rails and identical spacing between adjacent GATE stripes.
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Abstract
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
216 Citations
21 Claims
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1. A process for making a semiconductor wafer that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, and a gate contact (GATECNT) layer, the process comprising at least:
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(i) creating a first design of experiments (DOE) by instantiating, on the wafer, at least first and second non-contact electrical measurement (NCEM)-enabled fill cells in a standard cell form, with first and second supply rails that extend horizontally across the cells and uniformly spaced GATE stripes that extend vertically across the cells, said creating further including instantiating, on the wafer, test area patterning that comprises at least first and second features, arranged in a via open configuration, with the first feature electrically connected to an NCEM pad and the second feature electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area using a non-contact (NC) measurement at the NCEM pad, said creating further including providing at least one patterning difference between the first and second NCEM-enabled fill cells that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; and
,(ii) creating a second DOE by instantiating, on the wafer, at least first and second NCEM-enabled fill cells in a standard cell form, with first and second supply rails that extend horizontally across the cells and uniformly spaced GATE stripes that extend vertically across the cells, said creating further including instantiating, on the wafer, test area patterning that comprises at least first and second features, arranged in a stitch open configuration, with the first feature electrically connected to an NCEM pad and the second feature electrically connected to a permanent or virtual ground, thereby enabling detection of an unintended open or resistance in the test area using a NC measurement at the NCEM pad, said creating further including providing at least one patterning difference between the first and second NCEM-enabled fill cells that results in a different probability of detecting opens or resistances in the test area of the first NCEM-enabled fill cell versus the test area of the second NCEM-enabled fill cell; wherein creating the first and second DOEs further comprises instantiating all of the NCEM-enabled fill cells in the first and second DOEs in a compatible standard cell form, with identical spacing between the first and second supply rails and identical spacing between adjacent GATE stripes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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InventorsLam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
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Primary Examiner(s)Henry, Caleb
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Assistant Examiner(s)Belousov, Alexander
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Application NumberUS15/634,896Time in Patent Office105 DaysField of SearchUS Class CurrentCPC Class CodesG06F 11/079 Root cause analysis, i.e. e...G06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 2027/11875 Wiring region, routingH01L 22/14 for electrical parameters, ...H01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/34 Circuits for electrically c...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/11807 CMOS gate arraysH01L 29/0649 Dielectric regions, e.g. Si...H01L 29/0684 characterised by the shape,...H01L 29/41725 Source or drain electrodes ...
