Buried channel deeply depleted channel transistor

• US 9,786,703 B2
• Filed: 10/04/2016
• Issued: 10/10/2017
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Bakhishev, Teymur, Wang, Lingquan, Zhao, Dalong, Ranade, Pushkar, Thompson, Scott E.
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/285,308
• Publication Number:
  US 20170025457A1
• Time in Patent Office: 371 Days
• Field of Search: 257403, 257E2927, 257402
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having at least one device region of a first conductivity type;

a source region and a drain region of a second conductivity type formed in the at least one device region and separated by a channel length;

a channel region of the second conductivity type formed in the at least one device region between the source region and the drain region; and

a screening region of the first conductivity type formed in the at least one device region below the channel region and between the source region and the drain region, an effective doping density of the screening region being substantially higher than an effective doping density of the at least one device region; and

a gate structure formed on the at least one device region above the channel region,

wherein the channel region is modified, in response to a bias voltage at the gate structure, to provide a surface depletion layer below the gate structure, a buried depletion layer at an interface of the channel region and the screening region, and a buried channel layer between the surface depletion layer and the buried depletion layer electrically coupling the source region and the drain region, and

wherein the buried depletion layer is substantially located in channel region.

2. The semiconductor of claim 1 wherein the channel region has an effective doping density of the second conductivity type less than an effective doping density of the second conductivity type for the source region and the drain region and less than an effective doping density of the first conductivity type for the screening region.

3. The semiconductor device of claim 1, wherein the channel region has an effective doping density that is less than 1/10 of an effective doping density of the source region and the drain region.

4. The semiconductor of claim 1, wherein the screening region has an effective doping density of between about 10¹⁸ cm⁻

3 to 5×

10²⁰ cm<sup>−

3</sup>.

5. The semiconductor device of claim 1, wherein the buried depletion layer is completely located in the channel region.

6. The semiconductor device of claim 1, further comprising:

a gate control circuit, the gate control circuit comprising a reset transistor and a photodiode electrically coupled in series between a first reference voltage node and a second reference voltage node; and

an output circuit electrically coupled to the source region,

wherein the drain region is electrically coupled to a power supply node, and wherein the gate structure is electrically coupled to a portion of the gate control circuit between the reset transistor and the photodiode to define a gate control node.

7. The semiconductor device of claim 6, wherein the gate control circuit further comprises a transfer gate electrically coupled in series between the gate control node and the photodiode, and wherein the output circuit comprises a pass transistor.