Power semiconductor device
First Claim
1. A method for manufacturing a semiconductor device including a power MISFET having a super junction structure, comprising steps of:
- (a) providing a semiconductor substrate;
(b) forming a first n-type layer over the semiconductor substrate;
(c) selectively introducing impurities into the first n-type layer, thereby forming first and second p-type impurity regions in the first n-type layer;
(d) forming a second n-type layer over the first n-type layer, the first p-type impurity region and the second p-type impurity region;
(e) selectively introducing impurities into the second n-type layer, thereby forming third and fourth p-type impurity regions in the second n-type layer such that the first and third p-type impurity regions are connected and the second and fourth p-type impurity regions are connected;
(f) forming a body region of the power MISFET in the second n-type layer such that the body region is connected to a first p-type column and a second p-type column,(g) forming a source region of the power MISFET in the body region;
(h) forming a gate insulating film of the power MISFET over the second n-type layer; and
(i) forming a gate electrode of the power MISFET over the gate insulating film,wherein the first p-type column of the super junction structure comprises the first and third p-type impurity regions and extends in a first direction in a plan view,wherein the second p-type column of the super junction structure comprises the second and fourth p-type impurity regions and extends in the first direction in the plan view,wherein the second p-type column is arranged between the first p-type column and an edge of the semiconductor substrate in a second direction perpendicular to the first direction in the plan view, andwherein the second p-type column includes a larger impurity concentration portion than the first p-type column.
1 Assignment
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Accused Products
Abstract
A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.
28 Citations
6 Claims
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1. A method for manufacturing a semiconductor device including a power MISFET having a super junction structure, comprising steps of:
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(a) providing a semiconductor substrate; (b) forming a first n-type layer over the semiconductor substrate; (c) selectively introducing impurities into the first n-type layer, thereby forming first and second p-type impurity regions in the first n-type layer; (d) forming a second n-type layer over the first n-type layer, the first p-type impurity region and the second p-type impurity region; (e) selectively introducing impurities into the second n-type layer, thereby forming third and fourth p-type impurity regions in the second n-type layer such that the first and third p-type impurity regions are connected and the second and fourth p-type impurity regions are connected; (f) forming a body region of the power MISFET in the second n-type layer such that the body region is connected to a first p-type column and a second p-type column, (g) forming a source region of the power MISFET in the body region; (h) forming a gate insulating film of the power MISFET over the second n-type layer; and (i) forming a gate electrode of the power MISFET over the gate insulating film, wherein the first p-type column of the super junction structure comprises the first and third p-type impurity regions and extends in a first direction in a plan view, wherein the second p-type column of the super junction structure comprises the second and fourth p-type impurity regions and extends in the first direction in the plan view, wherein the second p-type column is arranged between the first p-type column and an edge of the semiconductor substrate in a second direction perpendicular to the first direction in the plan view, and wherein the second p-type column includes a larger impurity concentration portion than the first p-type column. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification