Method of forming horizontal gate all around structure

• US 9,786,757 B2
• Filed: 03/08/2016
• Issued: 10/10/2017
• Est. Priority Date: 11/04/2014
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Huan-Chieh, Huang, Jui-Chien, Lin, Chun-An, Wang, Chien-Hsun, Lin, Chun-Hsiung
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US15/063,601
• Publication Number:
  US 20160190272A1
• Time in Patent Office: 581 Days
• Field of Search: 438284, 257E21442
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a plurality of fins on a substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

forming dielectric material between the fins, the dielectric material exposing a portion of the fins above a first level; and

removing the top sacrificial layer and the bottom sacrificial layer above the first level.

2. The method of claim 1, wherein the dielectric material comprises shallow trench isolation material.

3. The method of claim 1, further comprising:

etching the dielectric material to expose the portion of the fins above the first level;

etching the dielectric material to expose a portion of the fins above a second level that is lower than the first level.

4. The method of claim 3, wherein a difference in height between the first and second levels is about 10-50 nanometers.

5. The method of claim 3, wherein the etching of the dielectric material to expose the portion of the fins above the first level comprises etching back the dielectric material to expose the top sacrificial layer of the fins.

6. The method of claim 3, wherein the etching of the dielectric material to expose the portion of the fins above the second level comprises etching back the dielectric material to expose the bottom sacrificial layer of the fins.

7. The method of claim 1, wherein the portion has a height that is less than about 50 nanometers.

8. The method of claim 1, further comprising:

oxidizing the top sacrificial layer and the bottom sacrificial layer.

9. A method of forming a semiconductor device, the method comprising:

forming a plurality of fins on a substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

providing dielectric material between the fins;

forming source and drain regions adjacent to the fins;

removing a portion of the top sacrificial layer and the bottom sacrificial layer; and

forming a gate around the top channel layer and the bottom channel layer.

10. The method of claim 9, further comprising:

forming a poly layer over a preset portion of the fins, wherein the source and drain regions are formed adjacent to the preset portion;

forming an interlayer dielectric layer over the source and drain regions;

forming a cap layer over the interlayer dielectric layer; and

removing the poly layer.

11. The method of claim 10, wherein the forming of the cap layer over the interlayer dielectric layer comprises:

etching back the interlayer dielectric layer;

forming a nitride layer over the poly layer and the interlayer dielectric layer; and

performing chemical mechanical polishing on the nitride layer and stopping at the poly layer.

12. The method of claim 11, wherein the nitride layer comprises at least one of SiN and SiCN.

13. A method of forming a semiconductor device, the method comprising:

forming a plurality of fins on a substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

providing dielectric material between the fins;

forming a poly layer over a preset portion of the fins;

forming source and drain regions adjacent to the preset portion;

removing the poly layer;

removing a portion of the top sacrificial layer and the bottom sacrificial layer; and

forming a gate around the top channel layer and the bottom channel layer.

14. The method of claim 13, further comprising:

forming an interlayer dielectric layer over the source and drain regions; and

forming a cap layer over the interlayer dielectric layer.

15. The method of claim 14, wherein the forming of the cap layer over the interlayer dielectric layer further comprises:

etching back the interlayer dielectric layer;

forming a nitride layer over the poly layer and the interlayer dielectric layer; and

performing chemical mechanical polishing on the nitride layer and stopping at the poly layer.

16. The method of claim 13, wherein the dielectric material comprises shallow trench isolation material.

17. The method of claim 13, wherein the providing of the dielectric material between the fins comprises:

forming the dielectric material between the fins; and

etching back the dielectric material to expose a portion of the fins.

18. The method of claim 13, wherein forming the source and drain regions comprises creating recesses in the fins for the source and drain regions.

19. The method of claim 13, further comprising:

forming a hard mask to protect a top of the poly layer; and

forming spacers to protect a sidewall of the poly layer.

20. The method of claim 13, wherein the forming of the fins on the substrate comprises forming the fins with (i) Si as the top channel layer and the bottom channel layer, and (ii) SiGe as the top sacrificial layer and the bottom sacrificial layer.