Semiconductor device

• US 9,786,778 B1
• Filed: 08/29/2016
• Issued: 10/10/2017
• Est. Priority Date: 05/30/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Morizuka, Kohei
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitry
• Application Number:
  US15/249,724
• Time in Patent Office: 407 Days
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device including a first electrode, a second electrode, and a silicon carbide layer of which at least a portion is provided between the first electrode and the second electrode, the silicon carbide layer including an n-type first silicon carbide region, a plurality of p-type second silicon carbide regions, and a plurality of n-type third silicon carbide regions. The semiconductor device further includes a plurality of first conductive layers each of which is in contact with the n-type first silicon carbide region, a number n, n being 2, 3, 4 or 5, of first gate electrodes that are provided between two adjacent first conductive layers of the plurality of first conductive layers, and extend in the first direction, and a plurality of first gate insulating layers each of which is provided between one of the n first gate electrodes and the n-type first silicon carbide region.

Claims

1. A semiconductor device, comprising:

a first electrode;

a second electrode;

a silicon carbide layer of which at least a portion is provided between the first electrode and the second electrode, the silicon carbide layer including

an n-type first silicon carbide region that is provided in the silicon carbide layer;

a plurality of p-type second silicon carbide regions that are each provided in the silicon carbide layer between the n-type first silicon carbide region and the first electrode, and extend in a first direction; and

a plurality of n-type third silicon carbide regions each of which is provided in the silicon carbide layer between one of the plurality of p-type second silicon carbide regions and the first electrode, has an n-type impurity concentration higher than an n-type impurity concentration of the n-type first silicon carbide region, and is electrically connected to the first electrode;

a plurality of first conductive layers each of which is in contact with the n-type first silicon carbide region between two adjacent p-type second silicon carbide regions of the plurality of p-type second silicon carbide regions, extends in the first direction, is provided in a first period, and is electrically connected to the first electrode;

a number n, n being 2, 3, 4 or 5, of first gate electrodes that are provided between two adjacent first conductive layers of the plurality of first conductive layers, and extend in the first direction; and

a plurality of first gate insulating layers each of which is provided between one of the n first gate electrodes and the n-type first silicon carbide region.

2. The device according to claim 1,

wherein a junction between each of the plurality of first conductive layers and the n-type first silicon carbide region is a hetero-junction or a Schottky junction.

3. The device according to claim 1, further comprising:

a plurality of p-type fourth silicon carbide regions each of which is provided in the silicon carbide layer between one of the plurality of p-type second silicon carbide regions and the first electrode, has a p-type impurity concentration higher than a p-type impurity concentration of the plurality of p-type second silicon carbide regions, and is electrically connected to the first electrode.

4. The device according to claim 1,

wherein the plurality of p-type second silicon carbide regions are provided in a second period that is approximately 1/(n+1) times the first period.

5. The device according to claim 1,

wherein the plurality of first conductive layers and the n first gate electrodes include n-type or p-type polycrystal silicon.

6. The device according to claim 1,

wherein the plurality of first conductive layers are a portion of the first electrode, and the n first gate electrodes include n-type or p-type polycrystal silicon.

7. The device according to claim 1, further comprising:

a third electrode that is electrically connected to the first electrode;

a plurality of p-type fifth silicon carbide regions that are each provided in the silicon carbide layer between the n-type first silicon carbide region and the third electrode, and extend in the first direction;

a plurality of n-type sixth silicon carbide regions each of which is provided in the silicon carbide layer between one of the plurality of p-type fifth silicon carbide regions and the third electrode, has an n-type impurity concentration higher than an n-type impurity concentration of the n-type first silicon carbide region, and is electrically connected to the third electrode;

a plurality of second conductive layers each of which is in contact with the n-type first silicon carbide region between two adjacent p-type fifth silicon carbide regions of the plurality of p-type fifth silicon carbide regions, extends in the first direction, is provided in the first period, and is electrically connected to the third electrode;

a number n, n being 2, 3, 4 or 5, of second gate electrodes which are provided between two adjacent second conductive layers of the plurality of second conductive layers, and extend in the first direction;

a plurality of second gate insulating layers each of which is provided between one of the n second gate electrodes and the n-type first silicon carbide region;

a gate layer that is provided between the n first gate electrodes and the n second gate electrodes, is connected to ends of the n first gate electrodes and ends of the n second gate electrodes, and is wider than the n first gate electrodes and the n second gate electrodes;

an insulating layer that is provided between the gate layer and the n-type first silicon carbide region, and is thicker than the plurality of first gate insulating layers and the plurality of second gate insulating layers; and

a p-type seventh silicon carbide region that is provided in the silicon carbide layer between the n-type first silicon carbide region and the insulating layer, is connected to at least a subset of the plurality of p-type second silicon carbide regions, and is connected to at least a subset of the plurality of p-type fifth silicon carbide regions.

8. The device according to claim 7,

wherein a distance between an arbitrary position of the p-type seventh silicon carbide region and a portion at which any one of two adjacent first conductive layers and the n-type first silicon carbide region are in contact with each other, or a portion at which any one of two adjacent second conductive layers and the n-type first silicon carbide region are in contact with each other is less than a half of 6/(n+1) times the first period.

9. The device according to claim 7,

wherein a distance between an arbitrary position of the p-type seventh silicon carbide region and a portion at which any one of two adjacent first conductive layers and the n-type first silicon carbide region are in contact with each other, or a portion at which any one of two adjacent second conductive layers and the n-type first silicon carbide region are in contact with each other, is less than a half of the first period.

10. The device according to claim 7,

wherein the plurality of first conductive layers and the plurality of second conductive layers are connected to each other.

11. The device according to claim 8,

wherein the plurality of first conductive layers and the plurality of second conductive layers are connected to each other.

12. The device according to claim 9,

wherein the plurality of first conductive layers and the plurality of second conductive layers are connected to each other.

13. The device according to claim 1, further comprising:

a third electrode that is electrically connected to the first electrode;

a plurality of p-type fifth silicon carbide regions that are each provided in the silicon carbide layer between the n-type first silicon carbide region and the third electrode, and extend in the first direction;

a plurality of n-type sixth silicon carbide regions each of which is provided in the silicon carbide layer between one of the plurality of p-type fifth silicon carbide regions and the third electrode, has an n-type impurity concentration higher than an n-type impurity concentration of the n-type first silicon carbide region, and is electrically connected to the third electrode;

a plurality of second conductive layers each of which is in contact with the n-type first silicon carbide region between two adjacent p-type fifth silicon carbide regions of the plurality of p-type fifth silicon carbide regions, extends in the first direction, is provided in the first period, and is electrically connected to the third electrode;

a number n, n being 2, 3, 4, or 5, of second gate electrodes which are provided between two adjacent second conductive layers of the plurality of second conductive layers, and extend in the first direction;

a plurality of second gate insulating layers each of which is provided between one of the n second gate electrodes and the n-type first silicon carbide region;

a gate layer that is provided between the n first gate electrodes and the n second gate electrodes, is connected to ends of the n first gate electrodes and ends of the n second gate electrodes, and is wider than the n first gate electrodes and the n second gate electrodes;

an insulating layer that is provided between the gate layer and the n-type first silicon carbide region, and is thicker than the plurality of first gate insulating layers and the plurality of second gate insulating layers; and

a p-type eighth silicon carbide region that is provided in the silicon carbide layer between the n-type first silicon carbide region and the insulating layer, is connected to at least a subset of the plurality of p-type second silicon carbide regions, is connected to at least a subset of the plurality of p-type fifth silicon carbide regions, and has a p-type impurity concentration lower than a p-type impurity concentration of the plurality of p-type second silicon carbide regions and the plurality of p-type fifth silicon carbide regions.

14. The device according to claim 13,

wherein a depth of the p-type eighth silicon carbide region in the silicon carbide layer is shallower than a depth of the plurality of p-type second silicon carbide regions in the silicon carbide layer and a depth of the plurality of p-type fifth silicon carbide regions in the silicon carbide layer.

15. The device according to claim 1, further comprising:

a third electrode that is connected to the first electrode;

a plurality of p-type fifth silicon carbide regions that are each provided in the silicon carbide layer between the n-type first silicon carbide region and the third electrode, and extend in the first direction;

a plurality of n-type sixth silicon carbide regions each of which is provided in the silicon carbide layer between one of the plurality of p-type fifth silicon carbide regions and the third electrode, has an n-type impurity concentration higher than an n-type impurity concentration of the n-type first silicon carbide region, and is electrically connected to the third electrode;

a plurality of second conductive layers each of which is in contact with the n-type first silicon carbide region between two adjacent p-type fifth silicon carbide regions of the plurality of p-type fifth silicon carbide regions, extends in the first direction, is provided in the first period, and is electrically connected to the third electrode;

a number n, n being 2, 3, 4, or 5, of second gate electrodes that are provided between two adjacent second conductive layers of the plurality of second conductive layers, and extend in the first direction;

a plurality of second gate insulating layers each of which is provided between one of the n second gate electrodes and the n-type first silicon carbide region;

a gate layer that is provided between the n first gate electrodes and the n second gate electrodes, is connected to ends of the n first gate electrodes and ends of the n second gate electrodes, and is wider than the n first gate electrodes and the n second gate electrodes;

an insulating layer that is provided between the gate layer and the n-type first silicon carbide region, and is thicker than the plurality of first gate insulating layers and the plurality of second gate insulating layers; and

a p-type ninth silicon carbide region that is provided in the silicon carbide layer, between the n-type first silicon carbide region and the insulating layer and between the plurality of p-type second silicon carbide regions and the plurality of p-type fifth silicon carbide regions, and is spaced away from the plurality of p-type second silicon carbide regions and the plurality of p-type fifth silicon carbide regions.

16. The device according to claim 15,

wherein a distance between each of the plurality of p-type second silicon carbide regions and the p-type ninth silicon carbide region is equal to or less than a distance between two adjacent p-type second silicon carbide regions of the plurality of p-type second silicon carbide regions, and a distance between each of the plurality of p-type fifth silicon carbide regions and the p-type ninth silicon carbide region is equal to or less than a distance between two adjacent p-type fifth silicon carbide regions of the plurality of p-type fifth silicon carbide regions.