Method of manufacturing an image sensor device

• US 9,786,856 B2
• Filed: 08/15/2016
• Issued: 10/10/2017
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: DPIX LLC (DpiX Holding LLC)
• Original Assignee: DPIX LLC (DpiX Holding LLC)
• Inventors: O'Rourke, Shawn Michael, Park, Byung-Kyu, Rodriquez, Robert
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US15/237,447
• Publication Number:
  US 20170054097A1
• Time in Patent Office: 421 Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H10K 30/30 comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
• CPC Class Codes: H10K 30/81 Electrodes
• CPC Class Codes: H10K 30/82 Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
• CPC Class Codes: H10K 30/88 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 39/32 Organic image sensors
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 71/611 using printing deposition, e.g. ink jet printing
• CPC Class Codes: Y02E 10/549 Organic PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the inter-layer dielectric layer; forming a metal layer the inter-layer dielectric and within the inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer; forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk heterojunction layer on the electron transport layer; forming a hole transport layer on the bulk heterojunction layer; and forming a top contact layer on the hole transport layer.

Claims

1. A method of manufacturing an image sensor device comprising:

providing a metalized thin film transistor layer form on a glass substrate;

forming a first inter-layer dielectric layer on the metalized thin film transistor layer;

forming a via through the first inter-layer dielectric layer;

forming a metal layer on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer;

forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer;

forming a via through the second inter-layer dielectric layer;

forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer;

forming an electron transport layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer;

forming a bulk heterojunction layer on an upper surface of the electron transport layer;

forming a hole transport layer on an upper surface of the bulk heterojunction layer; and

forming a top contact layer on an upper surface of the hole transport layer.

2. The method of claim 1, wherein the first and second inter-layer dielectric layers each comprise a SiON, Si₀₂, or SiN layer.

3. The method of claim 1, wherein the metal layer comprises a quad-layer metal stack layer.

4. The method of claim 1, wherein the conductive oxide layer comprises an ITO, IGZO, IZO, ITZO, or AZO layer.

5. The method of claim 1, wherein the electron transport layer comprises a work function tuning layer.

6. The method of claim 1, wherein the bulk heterojunction layer comprises a photoactive layer.

7. The method of claim 1, wherein the hole transport layer comprises a work function tuning layer.

8. The method of claim 1, wherein the top contact layer comprises an anode layer.

9. A method of manufacturing an image sensor device comprising:

providing a metalized thin film transistor layer form on a glass substrate;

forming a first inter-layer dielectric layer on the metalized thin film transistor layer;

forming a via through the first inter-layer dielectric layer;

forming a metal layer on an upper surface of the first inter-layer dielectric and within the first inter-layer dielectric layer via for contacting the metalized thin film transistor layer;

forming a second inter-layer dielectric layer on an upper surface of the metal layer and the first inter-layer dielectric layer;

forming a via through the second inter-layer dielectric layer;

forming a conductive oxide layer on an upper surface of the second inter-layer dielectric layer and within the second inter-layer dielectric layer via for contacting an upper surface of the metal layer;

forming a bank layer on an upper surface of the second inter-layer dielectric layer and the conductive oxide layer;

forming a via through the bank layer;

forming an electron transport layer on an upper surface of the bank layer and within the bank layer via to contact an upper surface of the conductive oxide layer;

forming a bulk heterojunction layer on an upper surface of the electron transport layer;

forming a hole transport layer on an upper surface of the bulk heterojunction layer; and

forming a top contact layer on an upper surface of the hole transport layer.

10. The method of claim 9, wherein the first and second inter-layer dielectric layers each comprise a SiON, Si₀₂, or SiN layer.

11. The method of claim 9, wherein the metal layer comprises a quad-layer metal stack layer.

12. The method of claim 9, wherein the conductive oxide layer comprises an ITO, IGZO, IZO, ITZO, or AZO layer.

13. The method of claim 9, wherein the bank layer comprises a resin layer.

14. The method of claim 9, wherein the electron transport layer comprises a work function tuning layer.

15. The method of claim 9, wherein the bulk heterojunction layer comprises a photoactive layer.

16. The method of claim 9, wherein the hole transport layer comprises a work function tuning layer.

17. The method of claim 9, wherein the top contact layer comprises an anode layer.