Power integrated circuit with autonomous limit checking of ADC channel measurements
First Claim
1. An integrated circuit, comprising:
- a first terminal;
a second terminal;
a current switch circuit that can receive a current of up to a maximum input current from the first terminal, wherein the current switch circuit can conduct a through-current from the first terminal, through the current switch circuit to the second terminal with a resistance, and wherein the current switch circuit outputs a current sense voltage whose magnitude is indicative of a magnitude of a current flowing through the current switch circuit;
an input analog multiplexer circuit having a first analog input lead, a second analog input lead, at least one select input lead, and an analog output lead, wherein the first analog input lead is coupled to receive the current sense voltage, and wherein the second analog input lead is coupled to receive an input voltage;
an Analog-to-Digital Converter (ADC) that is coupled to the output lead of the input analog multiplexer circuit, wherein the ADC is adapted to output a first digital value indicative of a magnitude of the current flowing through the current switch circuit, and wherein the ADC is adapted to output a second digital value indicative of a magnitude of the input voltage;
a first comparator circuit adapted to compare the first digital value to a first limit value and to output a first comparison signal indicative of the comparison;
a second comparator circuit adapted to compare the second digital value to a second limit value and to output a second comparison signal indicative of the comparison; and
a third terminal adapted to output a flag signal, wherein the flag signal is indicative of a condition in which either the first comparison signal is asserted or the second comparison signal is asserted.
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Accused Products
Abstract
A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
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Citations
20 Claims
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1. An integrated circuit, comprising:
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a first terminal; a second terminal; a current switch circuit that can receive a current of up to a maximum input current from the first terminal, wherein the current switch circuit can conduct a through-current from the first terminal, through the current switch circuit to the second terminal with a resistance, and wherein the current switch circuit outputs a current sense voltage whose magnitude is indicative of a magnitude of a current flowing through the current switch circuit; an input analog multiplexer circuit having a first analog input lead, a second analog input lead, at least one select input lead, and an analog output lead, wherein the first analog input lead is coupled to receive the current sense voltage, and wherein the second analog input lead is coupled to receive an input voltage; an Analog-to-Digital Converter (ADC) that is coupled to the output lead of the input analog multiplexer circuit, wherein the ADC is adapted to output a first digital value indicative of a magnitude of the current flowing through the current switch circuit, and wherein the ADC is adapted to output a second digital value indicative of a magnitude of the input voltage; a first comparator circuit adapted to compare the first digital value to a first limit value and to output a first comparison signal indicative of the comparison; a second comparator circuit adapted to compare the second digital value to a second limit value and to output a second comparison signal indicative of the comparison; and a third terminal adapted to output a flag signal, wherein the flag signal is indicative of a condition in which either the first comparison signal is asserted or the second comparison signal is asserted. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit, comprising:
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a first terminal; a second terminal; an eFuse circuit that can receive a current from the first terminal and can conduct the current to the second terminal; and an autonomous limit checking circuit comprising an input analog multiplexer circuit, an Analog-to-Digital Converter (ADC) coupled to an output lead of the input analog multiplexer circuit, a digital state machine that controls the input analog multiplexer circuit, and a plurality of compare-and-mask circuits, wherein each compare-and-mask circuit comprises a capture register, a lower limit register, and an upper limit register, wherein the compare-and-mask circuit is adapted to compare a digital value stored in its capture register to a lower limit value stored in its lower limit register and to compare the digital value stored in its capture register to an upper limit value stored in its upper limit register, wherein the compare-and-mask circuit is adapted to assert a digital output signal indicative of a comparison performed by the compare-and-mask circuit. - View Dependent Claims (14, 15, 16, 17, 18)
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19. An integrated circuit, comprising:
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a first terminal; a second terminal; an eFuse means for receiving a current from the first terminal and for conducting the current to the second terminal in a non-fault condition, and for opening in a fault condition; and means for autonomously limit checking a plurality of voltages, for generating a digital value indicative of a magnitude of each such voltage, for each such voltage comparing the corresponding digital value to an upper limit value and comparing the corresponding digital value to a lower limit value, and for asserting a digital output signal indicative of a comparison pertaining to the corresponding digital value. - View Dependent Claims (20)
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Specification