Memory system and method of controlling nonvolatile memory

• US 9,792,068 B2
• Filed: 02/25/2016
• Issued: 10/17/2017
• Est. Priority Date: 09/10/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Nagata, Yuki
• Primary Examiner(s): King, Douglas
• Application Number:
  US15/052,995
• Publication Number:
  US 20170075580A1
• Time in Patent Office: 600 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

According to one embodiment, when a first command and first data are received from a host, and in a case where the number of free blocks is less than a first threshold, a controller executes a first processing. The first processing includes reading valid data included in one first block that includes the valid data and invalid data and writing the read valid data and at least a part of write data specified by the write command into the free block.

Claims

1. A memory system comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to

upon detecting a number of free blocks among the plurality of blocks being less than a first threshold, execute a first processing, the first processing including reading valid data from a plurality of first blocks among the plurality of blocks and writing the read valid data into a first free block among the free blocks, the first block including valid data and invalid data, each of the free blocks not including valid data,

upon detecting the number of the free blocks being less than a second threshold, execute a second processing, the second processing including reading valid data included in one first second block among the plurality of blocks and writing the read valid data and at least a part of first data into a second free block among the free blocks, the second block including valid data and invalid data, the first data being write data specified by a first command, the first command being a write command received from a host, the second threshold being smaller than the first threshold.

2. The memory system according to claim 1, wherein the controller is configured to execute a third processing when a second command is received from the host, the second command including an instruction to execute a garbage collection, the third processing including reading valid data from a plurality of third blocks among the plurality of blocks and writing the read valid data into a third free block among the free blocks, the third blocks including valid data and invalid data.

3. The memory system according to claim 2, wherein the third processing includes erasing data of the plurality of the third blocks from which the valid data is read.

4. The memory system according to claim 2, wherein the controller executes the third processing after the execution of the second processing.

5. The memory system according to claim 2, wherein

in the third processing, the controller preferentially selects, as the third block from the plurality of blocks, a fourth block rather than a fifth block, the fourth block including less valid data than the fifth block.

6. The memory system according to claim 1, wherein, when the first command and the first data are received from the host, and in a case where the number of the free blocks is more than the second threshold, the controller writes only the first data into the second free block.

7. The memory system according to claim 1, wherein, in a case where the number of the free blocks is less than a third threshold during execution of a fourth processing, the controller executes the first processing, the fourth processing including reading valid data stored in the nonvolatile memory and testing the read valid data.

8. The memory system according to claim 1, wherein, in a case where the number of the free blocks is two or more, the second processing includes writing the read valid data and at least a part of the first data into one second free block among the free blocks.

9. The memory system according to claim 1, wherein the second block includes more valid data than invalid data.

10. The memory system according to claim 1, wherein the nonvolatile memory is a NAND flash memory.

11. A method of controlling a nonvolatile memory including a plurality of blocks, the method comprising:

upon detecting a number of free blocks among the plurality of blocks being less than a first threshold, executing a first processing, the first processing including reading valid data from a plurality of first blocks among the plurality of blocks and writing the read valid data into a first free block among the free blocks, the first block including valid data and invalid data, each of the free blocks not including valid data,

upon detecting the number of the free blocks being less than a second threshold, executing a second processing, the second processing including reading valid data included in one first second block among the plurality of blocks and writing the read valid data and at least a part of first data into a second free block among the free blocks, the second block including valid data and invalid data, the first data being write data specified by a first command, the first command being a write command received from a host, the second threshold being smaller than the first threshold.

12. The method according to claim 11, further comprising executing a third processing when a second command is received from the host, the second command including an instruction to execute a garbage collection, the third processing including reading valid data from a plurality of third blocks among the plurality of blocks and writing the read valid data into a third free block among the free blocks, each of the third blocks including valid data and invalid data.

13. The method according to claim 12, wherein the third processing includes erasing data of the plurality of third blocks from which the valid data is read.

14. The method according to claim 12, further comprising executing the third processing after the execution of the second processing.

15. The method according to claim 12, further comprising

in the third processing, preferentially selecting, as the third block from the plurality of blocks, a fourth block rather than a fifth block, the fourth block including less valid data than the fifth block.

16. The method according to claim 11, further comprising

when the first command and the first data are received from the host, and in a case where the number of the free blocks is more than the second threshold, writing only the first data into the second free block.

17. The method according to claim 11, further comprising

in a case where the number of the free blocks is less than a third threshold during execution of a fourth processing, executing the first processing, the fourth processing including reading valid data stored in the nonvolatile memory and testing the read valid data.

18. The method according to claim 11, wherein, in a case where the number of the free blocks is two or more, the second processing includes writing the read valid data and at least a part of the first data into one second free block among the free blocks.

19. The method according to claim 11,

wherein the second block includes more valid data than invalid data.

20. The method according to claim 11, wherein the nonvolatile memory is a NAND flash memory.