Loading values from a value vector into subregisters of a single instruction multiple data register
First Claim
1. A processor that, within the processor, loads values from a vector of values into a series of subregisters of a SIMD register:
- wherein values within the vector of values are contiguous;
wherein each value in the vector of values is represented by a fixed number of bits;
wherein the fixed number of bits used to represent every value in the vector of values is the same;
wherein the processor is configured to respond to one or more instructions by;
based on the one or more instructions, subdividing the SIMD register into the series of subregisters;
wherein each subregister in the series of subregisters holds a greater number of bits than the fixed number of bits;
loading each subregister, of the series of subregisters, with a corresponding portion of the vector of values;
wherein loading each subregister includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters;
wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value;
after loading each subregister with the corresponding portion of the vector of values, performing a plurality of subregister shifting operations;
wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters;
wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters;
wherein the first amount is different than the second amount;
wherein the plurality of subregister shifting operations causes one of;
the first value to be aligned, in the first subregister, with a left boundary of the first subregister and the second value to be aligned, in the second subregister, with a left boundary of the second subregister,the first value to be aligned, in the first subregister, with a right boundary of the first subregister and the second value to be aligned, in the second subregister, with a right boundary of the second subregister, orthe first value and the second value to be byte-aligned; and
setting to zero all bits in the first subregister other than bits storing the first value; and
setting to zero all bits in the second subregister other than bits storing the second value.
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Accused Products
Abstract
A method and apparatus for efficiently processing data in various formats in a single instruction multiple data (“SIMD”) architecture is presented. Specifically, a method to unpack a fixed-width bit values in a bit stream to a fixed width byte stream in a SIMD architecture is presented. A method to unpack variable-length byte packed values in a byte stream in a SIMD architecture is presented. A method to decompress a run length encoded compressed bit-vector in a SIMD architecture is presented. A method to return the offset of each bit set to one in a bit-vector in a SIMD architecture is presented. A method to fetch bits from a bit-vector at specified offsets relative to a base in a SIMD architecture is presented. A method to compare values stored in two SIMD registers is presented.
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Citations
14 Claims
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1. A processor that, within the processor, loads values from a vector of values into a series of subregisters of a SIMD register:
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wherein values within the vector of values are contiguous; wherein each value in the vector of values is represented by a fixed number of bits; wherein the fixed number of bits used to represent every value in the vector of values is the same; wherein the processor is configured to respond to one or more instructions by; based on the one or more instructions, subdividing the SIMD register into the series of subregisters; wherein each subregister in the series of subregisters holds a greater number of bits than the fixed number of bits; loading each subregister, of the series of subregisters, with a corresponding portion of the vector of values; wherein loading each subregister includes loading the same portion of the vector of values into both a first subregister and a second subregister of the series of subregisters; wherein the portion of the vector of values that is loaded into both the first subregister and the second subregister includes both a first value and a second value; after loading each subregister with the corresponding portion of the vector of values, performing a plurality of subregister shifting operations; wherein the plurality of subregister shifting operations includes a first subregister shifting operation that shifts, by a first amount, the first subregister of the series of subregisters; wherein the plurality of subregister shifting operations includes a second subregister shifting operation that shifts, by a second amount, the second subregister of the series of subregisters; wherein the first amount is different than the second amount; wherein the plurality of subregister shifting operations causes one of; the first value to be aligned, in the first subregister, with a left boundary of the first subregister and the second value to be aligned, in the second subregister, with a left boundary of the second subregister, the first value to be aligned, in the first subregister, with a right boundary of the first subregister and the second value to be aligned, in the second subregister, with a right boundary of the second subregister, or the first value and the second value to be byte-aligned; and setting to zero all bits in the first subregister other than bits storing the first value; and setting to zero all bits in the second subregister other than bits storing the second value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processor configured to:
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load each subregister of a first series of subregisters in a first SIMD register with a corresponding length-representing-value from a vector of length-representing-values; wherein the first SIMD register resides within the processor; wherein each length-representing-value in the vector of length-representing-values corresponds to a value in a vector of values, and indicates length of the corresponding value in the vector of values; load values from the vector of values into a second series of subregisters of a second SIMD register that resides within the processor; wherein, prior to being loaded into the second series of subregisters, values within the vector of values are contiguous; wherein the values in the vector of values vary in length relative to each other; and wherein loading values from the vector of values into the second series of subregisters includes; based on one or more instructions, subdividing the second SIMD register into the second series of subregisters, wherein each subregister in the second series of subregisters is the same size; and for each value in the vector of values, performing the steps of; determining which length-representing-value, in the first series of subregisters, corresponds to the value; based on the length-representing-value that corresponds to the value, determining which portion of the vector of values corresponds to the value; and loading the portion of the vector of values that corresponds to the value from the vector of values into a corresponding subregister of the second series of subregisters. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification