Memory system and method of controlling nonvolatile memory

• US 9,792,172 B2
• Filed: 11/23/2015
• Issued: 10/17/2017
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kanno, Shinichi
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/948,649
• Publication Number:
  US 20170024276A1
• Time in Patent Office: 694 Days
• Field of Search: 714763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.

Claims

1. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to;

manage a plurality of namespaces for storing a plurality of kinds of data having different update frequencies, the namespaces including a first namespace for storing a first type of data and a second namespace for storing a second type of data having a lower update frequency than the first type of data,

encode first write data associated with an ID of the first namespace by using first coding for reducing wear of a memory cell to generate first encoded data having a first length,

generate second encoded data by adding a first error correction code having a second length to the first encoded data, the second encoded data including the first encoded data having the first length and the first error correction code having the second length,

write the second encoded data to the first namespace of the nonvolatile memory,

encode second write data associated with an ID of the second namespace by using the first coding for reducing wear of a memory cell to generate third encoded data having a third length less than the first length,

generate fourth encoded data by adding a second error correction code having a fourth length greater than the second length to the third encoded data, the fourth encoded data including the third encoded data having the third length and the second error correction code having the fourth length, and

write the fourth encoded data to the second namespace of the nonvolatile memory.

2. The memory system of claim 1, wherein the encoding the first write data includes converting a first code in the first write data into another code longer than the first code.

3. The memory system of claim 1, wherein the controller is configured to compress the first write data, and encode the compressed first write data by using the first coding to generate the first encoded data.

4. The memory system of claim 3, wherein the first encoded data is longer than the compressed first write data.

5. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to;

logically divide the nonvolatile memory into a plurality of areas for storing a plurality of kinds of data having different update frequencies, the plurality of areas being associated with a plurality of namespaces, the plurality of areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data, the first area and the second area being associated with a first namespace and a second namespace,

encode first write data associated with an ID of the first namespace by using first coding for reducing wear of a memory cell to generate first encoded data having a first length,

generate second encoded data by adding a first error correction code having a second length to the first encoded data, the second encoded data including the first encoded data having the first length and the first error correction code having the second length,

write the second encoded data to the first area,

encode second write data associated with an ID of the second namespace by using the first coding for reducing wear of a memory cell to generate third encoded data having a third length less than the first length,

generate fourth encoded data by adding a second error correction code having a fourth length greater than the second length to the third encoded data, the fourth encoded data including the third encoded data having the third length and the second error correction code having the fourth length, and

write the fourth encoded data to the second area.

6. A method of controlling a nonvolatile memory, the method comprising:

creating a plurality of namespaces for storing a plurality of kinds of data having different update frequencies, the namespaces including a first namespace for storing a first type of data and a second namespace for storing a second type of data having a lower update frequency than the first type of data;

encoding first write data associated with an ID of the first namespace by using first coding for reducing wear of a memory cell to generate first encoded data having a first length;

generating second encoded data by adding a first error correction code having a second length to the first encoded data, the second encoded data including the first encoded data having the first length and the first error correction code having the second length;

writing the second encoded data to the first namespace of the nonvolatile memory;

encoding second write data associated with an ID of the second namespace by using the first coding for reducing wear of a memory cell to generate third encoded data having a third length less than the first length;

generating fourth encoded data by adding a second error correction code having a fourth length greater than the second length to the third encoded data, the fourth encoded data including the third encoded data having the third length and the second error correction code having the fourth length; and

writing the fourth encoded data to the second namespace of the nonvolatile memory.

7. The method of claim 6, wherein the encoding the first write data includes converting a first code in the first write data into another code longer than the first code.

8. The method of claim 6, further comprising:

compressing the first write data, wherein

the first encoded data is generated by encoding the compressed first write data by using the first coding.

9. The method of claim 8, wherein the first encoded data is longer than the compressed first write data.