Resistive random access memory device

• US 9,792,987 B1
• Filed: 07/21/2016
• Issued: 10/17/2017
• Est. Priority Date: 07/21/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Chung-Cheng, Chih, Yue-Der, Chu, Wen-Ting
• Primary Examiner(s): Hoang, Tri
• Application Number:
  US15/216,520
• Time in Patent Office: 453 Days
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A memory architecture comprises a first memory macro comprising a first plurality of memory cells, a second memory macro comprising a second plurality of memory cells, and a control logic coupled to the first and second memory macros. The control logic is configured to write a logical state to each of the first and second pluralities of memory cells by using first and second signal levels, respectively, thereby causing the first and second memory macros to be used in first and second applications, respectively, the first and second signal levels being different and the first and second applications being different. The first and second memory macros are formed on a single chip, and wherein the first and second pluralities of the memory cells comprise a variable resistance dielectric layer formed using a single process recipe.

Claims

1. A memory architecture, comprising:

a first memory macro comprising a first plurality of memory cells;

a second memory macro comprising a second plurality of memory cells; and

a control logic, coupled to the first and second memory macros, and configured to transition each of the first and second pluralities of memory cells to either a first or a second logical state by using first and second signal levels, respectively, thereby causing the first and second memory macros to have first and second endurances, respectively, the first and second signal levels being different and the first and second endurances being different,

wherein the first and second memory macros are formed on a single chip, and wherein the first and second pluralities of the memory cells comprise a variable resistance dielectric layer formed using a single process recipe, and

wherein the first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between the first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.

2. The architecture of claim 1 wherein the first memory macro comprises a resistive random access memory (RRAM) macro, the first plurality of memory cells comprise a first plurality of RRAM cells, the second memory macro comprises an RRAM macro, the second plurality of memory cells comprise a second plurality of RRAM cells.

3. The architecture of claim 1 wherein the first logical state comprises logical 1 and the second logical state comprises logical 0.

4. The architecture of claim 3 wherein when the control logic writes the logical 1 to the memory cell, the control logic uses a voltage signal with a first polarity, and when the control logic writes the logical 0 to the memory cell, the control logic uses the voltage signal with a second polarity that is opposite to the first polarity.

5. The architecture of claim 1 wherein the first memory macro further comprises:

a first bit line (BL) driver coupled to the first plurality of memory cells and the control logic;

a first word line (WL) driver coupled to the first plurality of memory cells and the control logic; and

a first multiplexer coupled between the first plurality of memory cells and the first BL driver, and the control logic.

6. The architecture of claim 5 wherein the second memory macro further comprises:

a second bit line (BL) driver coupled to the second plurality of memory cells and the control logic;

a second word line (WL) driver coupled to the second plurality of memory cells and the control logic; and

a second multiplexer coupled between the second plurality of memory cells and the second BL driver, and the control logic.

7. The architecture of claim 6 wherein the first and second BL drivers, the first and second WL drivers, the first and second multiplexers are different from each other, respectively.

8. The architecture of claim 1 further comprising:

a third memory macro comprising a third plurality of memory cells, wherein the control logic is configured to transition each of the third plurality of memory cells into either the first or second logical state by using a third signal level, the third signal level being different from the first and second signal levels, wherein the third memory macro is formed on the single chip, and wherein each of the third plurality of memory cells comprises the substantially identical variable resistance dielectric layer.

9. The architecture of claim 1 further comprising:

a signal source, coupled between the control logic and the first and second memory macros, and configured to provide voltage signals with the first and second signal levels to the first and second pluralities of memory cells, respectively.

10. The architecture of claim 1 wherein the control logic is configured to simultaneously write a logical state to each of the first and second pluralities of memory cells by using first and second signal levels, respectively.

11. A resistive random access memory (RRAM) architecture, comprising:

a first RRAM cell array comprising a first plurality of RRAM cells;

a second RRAM cell array, comprising a second plurality of RRAM cells, and coupled to the first RRAM cell array;

a bit line (BL) driver coupled to the first and second RRAM cell arrays; and

a control logic, coupled to the first RRAM cell array, the second RRAM cell array, and the BL driver, and configured to transition each of the first and second pluralities of RRAM cells to either a first or a second logical state through the BL driver by using first and second signal levels, respectively, thereby causing the first and second RRAM cell arrays to have first and second endurances, respectively, the first and second signal levels and the first and second endurances being different,

wherein the first and second RRAM cell arrays are formed as an RRAM macro on a single chip, and wherein the first and second pluralities of the RRAM cells comprise a substantially identical variable resistance dielectric layer, and

wherein the first endurance comprises a maximum number of cycles for which the first plurality of RRAM cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.

12. The architecture of claim 11 wherein the variable resistance dielectric layer comprises a thickness and crystalline structure that is formed by using a single recipe of deposition equipment.

13. The architecture of claim 11 wherein when the control logic writes logical 1 of the logical state to the RRAM cell, the control logic uses a voltage signal with a first polarity, and when the control logic writes logical 0 of the logical state to the RRAM cell, the control logic uses the voltage signal with a second polarity that is opposite to the first polarity.

14. The architecture of claim 11 wherein the RRAM macro further comprises:

a first word line (WL) driver coupled between the first plurality of RRAM cells and the control logic.

15. The architecture of claim 14 wherein the RRAM macro further comprises:

a second word line (WL) driver coupled between the second plurality of RRAM cells and the control logic, the second WL driver being different from the first WL driver.

16. The architecture of claim 11 wherein the BL driver further comprises a multiplexer coupled to the control logic.

17. The architecture of claim 11 wherein the control logic is further configured to write the first logical state to the first plurality of RRAM cells by using the first signal level, and subsequently write the first logical state to the second plurality of RRAM cells by using the second signal level.

18. A method of forming a memory, comprising:

providing at least two cell arrays;

providing a universal variable resistance dielectric layer on the at least two cell arrays;

selecting a first cell array to have a first endurance;

selecting a second cell array to have a second endurance;

transitioning the first cell array to either a first or a second logical state using a first signal level; and

transitioning the second cell array to either the first or the second logical state using a second signal level.

19. The method of claim 18 wherein the first signal level is different form the second signal level.

20. The method of claim 18 wherein the transitioning the first cell array to either the first or the second logical state occurs simultaneously with the transitioning the second cell array to either the first or the second logical state.