Memory cell with high endurance for multiple program operations

• US 9,792,993 B2
• Filed: 01/16/2017
• Issued: 10/17/2017
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lo, Chun-Yuan, Wang, Shih-Chen, Ching, Wen-Hao
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US15/406,802
• Publication Number:
  US 20170206969A1
• Time in Patent Office: 274 Days
• Field of Search: 36518523, 36518518, 36518529, 36518513, 36518503, 3651851, 36518517, 36518526, 36518527, 36518528, 36523006, 36518501, 36518502, 36518505, 36518511
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

Claims

1. A memory cell comprising:

a read select transistor having a first terminal coupled to a bit line, a second terminal, a control terminal coupled to a word line, and a body terminal coupled to a source line;

a first floating gate transistor having a first terminal coupled to the second terminal of the read transistor, a second terminal coupled to the source line, and a body terminal coupled to the source line;

a program select transistor having a first terminal coupled to an erase control line, a second terminal, a control terminal coupled to an operation control line, and a body terminal coupled to the erase control line;

a second floating gate transistor having a first terminal coupled to the second terminal of the program transistor, a second terminal, and a body terminal coupled to the erase control line; and

a common floating gate coupled to the first floating gate transistor and the second floating gate transistor.

2. The memory cell of claim 1, wherein a first overlap area on a first oxide diffusion region overlapping the common floating gate is greater than a second overlap area on a second oxide diffusion region overlapping the common floating gate.

3. The memory cell of claim 1, wherein the read transistor, the first floating gate transistor, the program transistor, and the second floating gate transistor are formed by P-type metal-oxide-semiconductors (PMOS).

4. The memory cell of claim 3, wherein:

the read select transistor and the first floating gate transistor are formed in a first N-well; and

the program select transistor and the second floating gate transistor are formed in a second N-well.

5. The memory cell of claim 3, wherein during a program operation of the memory cell:

the source line is at a first voltage (0V);

the bit line is at the first voltage (0V);

the word line is at the first voltage (0V);

the operation control line is at a second voltage (10V); and

the erase control line is at a third voltage (18V);

wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.

6. The memory cell of claim 5, wherein during a read operation of the memory cell:

the source line is at a fourth voltage (5V);

the bit line is at a fifth voltage (3.8V);

the word line is at the first voltage (0V);

the operation control line is at the first voltage (0V); and

the erase control line is at the first voltage (0V);

wherein the second voltage is greater than the fourth voltage, the fourth voltage is greater than the fifth voltage, and the fifth voltage is greater than the first voltage.

7. The memory cell of claim 3, wherein during an erase operation of the memory cell:

the source line is at a third voltage (18V);

the bit line is at a second voltage (10V);

the word line is at the third voltage (18V);

the operation control line is at a first voltage or the second voltage (10V); and

the erase control line is at the first voltage (0V);

wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.

8. The memory cell of claim 1, wherein the read transistor, the first floating gate transistor, the program transistor, and the second floating gate transistor are formed by N-type metal-oxide-semiconductors (NMOS).

9. The memory cell of claim 8, wherein:

the read select transistor and the first floating gate transistor are formed in a first P-well;

the program select transistor and the second floating gate transistor are formed in a second P-well; and

the first P-well and the second P-well are disposed in a deep N-well.

10. A memory array comprising:

a plurality of bit lines;

a plurality of word lines;

a plurality of operation control lines;

a plurality of erase control lines;

a plurality of source lines; and

a plurality of rows of memory cells, each comprising;

a read select transistor having a first terminal coupled to a bit line of the plurality of bit lines, a second terminal, a control terminal coupled to a word line of the plurality of word lines, and a body terminal coupled to a source line of the plurality of source lines;

a first floating gate transistor having a first terminal coupled to the second terminal of the read transistor, a second terminal coupled to the source line, and a body terminal coupled to the source line;

a program select transistor having a first terminal coupled to an erase control line of the plurality of erase control lines, a second terminal, a control terminal coupled to an operation control line of the plurality of operation control lines, and a body terminal coupled to the erase control line;

a second floating gate transistor having a first terminal coupled to the second terminal of the program transistor, a second terminal, and a body terminal coupled to the erase control line; and

a common floating gate coupled to the first floating gate transistor and the second floating gate transistor;

wherein;

memory cells in a same row are coupled to a same word line, a same source line, and a same erase control line; and

memory cells in a same column are coupled to a same bit line, and a same operation control line.

11. The memory array of claim 10, wherein a first overlap area on a first oxide diffusion region overlapping the common floating gate is greater than a second overlap area on a second oxide diffusion region overlapping the common floating gate.

12. The memory array of claim 10, wherein the read transistor, the first floating gate transistor, the program transistor, and the second floating gate transistor are formed by P-type metal-oxide-semiconductors (PMOS).

13. The memory array of claim 12, wherein:

the read select transistor and the first floating gate transistor are formed in a first N-well; and

the program select transistor and the second floating gate transistor are formed in a second N-well.

14. The memory array of claim 12, wherein during a program operation of the memory cell:

the source line is at a first voltage (0V);

the bit line is at the first voltage (0V);

the word line is at the first voltage (0V);

the operation control line is at a second voltage (10V); and

the erase control line is at a third voltage (18V);

wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.

15. The memory array of claim 14, wherein during the program operation of the memory cell:

a bit line coupled to an unselected memory cell in a same row as the memory cell is at the first voltage (0V); and

an operation control line coupled to the unselected memory cell is at the third voltage (18V).

16. The memory array of claim 14, wherein during the program operation of the memory cell:

a word line coupled to an unselected memory cell in a same column as the memory cell is at the first voltage (0V);

a source line coupled to the unselected memory cell is at the first voltage (0V); and

an erase control line coupled to the unselected memory cell is at the second voltage (10V).

17. The memory array of claim 14, wherein during a read operation of the memory cell:

the source line is at a fourth voltage (5V);

the bit line is at a fifth voltage (3.8V);

the word line is at the first voltage (0V);

the operation control line is at the first voltage (0V); and

the erase control line is at the first voltage (0V);

wherein the second voltage is greater than the fourth voltage, the fourth voltage is greater than the fifth voltage, and the fifth voltage is greater than the first voltage.

18. The memory array of claim 17, wherein during the read operation of the memory cell:

a bit line coupled to an unselected memory cell in a same row as the memory cell is at the first voltage (0V); and

an operation control line coupled to the unselected memory cell is at the first voltage (0V).

19. The memory array of claim 17, wherein during the read operation of the memory cell:

a word line coupled to an unselected memory cell in a same column as the memory cell is at the fourth voltage (5V);

a source line coupled to the unselected memory cell is at the first voltage (0V); and

an erase control line coupled to the unselected memory cell is at the first voltage (0V).

20. The memory array of claim 12, wherein during an erase operation of the memory cell:

the source line is at a third voltage (18V);

the bit line is at a second voltage (10V);

the word line is at the third voltage (18V);

the operation control line is at a first voltage (0V) or the second voltage (10V); and

the erase control line is at the first voltage (0V);

wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.

21. The memory array of claim 20, wherein during the erase operation of the memory cell:

a word line coupled to an unselected memory cell in a same column as the memory cell is at the third voltage (18V);

a source line coupled to the unselected memory cell is at the second voltage (10V); and

an erase control line coupled to the unselected memory cell is at the first voltage (0V).

22. The memory array of claim 10, wherein the read transistor, the first floating gate transistor, the program transistor, and the second floating gate transistor are formed by N-type metal-oxide-semiconductors (NMOS).

23. The memory array of claim 22, wherein:

the read select transistor and the first floating gate transistor are formed in a first P-well;

the program select transistor and the second floating gate transistor are formed in a second P-well; and

the first P-well and the second P-well are disposed in a deep N-well.