Independent multi-plane read and low latency hybrid read
First Claim
1. An apparatus, comprising:
- multiple planes of memory cells, wherein the multiple planes comprise a first plane and a second plane;
a first set of registers;
a second set of registers;
an external controller configured to provide a sequence of read commands for a selected word line of the first plane and a sequence of read commands for a selected word line of the second plane, to update values in the first set of registers with each read command for the selected word line of the first plane, and to update values in the second set of registers with each read command for the selected word line of the second plane; and
a state machine coupled to the external controller, the state machine is configured to;
in response to each of the read commands for the selected word line of the first plane, read the updated values from the first set of registers, and provide read voltages on the selected word line in the first plane according to an order of the updated values in the first set of registers, andin response to each of the read commands for the selected word line of the second plane, read the updated values from the second set of registers, and provide read voltages on the selected word line in the second plane according to an order of the updated values in the second set of registers.
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Accused Products
Abstract
Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.
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Citations
6 Claims
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1. An apparatus, comprising:
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multiple planes of memory cells, wherein the multiple planes comprise a first plane and a second plane; a first set of registers; a second set of registers; an external controller configured to provide a sequence of read commands for a selected word line of the first plane and a sequence of read commands for a selected word line of the second plane, to update values in the first set of registers with each read command for the selected word line of the first plane, and to update values in the second set of registers with each read command for the selected word line of the second plane; and a state machine coupled to the external controller, the state machine is configured to; in response to each of the read commands for the selected word line of the first plane, read the updated values from the first set of registers, and provide read voltages on the selected word line in the first plane according to an order of the updated values in the first set of registers, and in response to each of the read commands for the selected word line of the second plane, read the updated values from the second set of registers, and provide read voltages on the selected word line in the second plane according to an order of the updated values in the second set of registers. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification