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Independent multi-plane read and low latency hybrid read

  • US 9,792,995 B1
  • Filed: 04/26/2016
  • Issued: 10/17/2017
  • Est. Priority Date: 04/26/2016
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • multiple planes of memory cells, wherein the multiple planes comprise a first plane and a second plane;

    a first set of registers;

    a second set of registers;

    an external controller configured to provide a sequence of read commands for a selected word line of the first plane and a sequence of read commands for a selected word line of the second plane, to update values in the first set of registers with each read command for the selected word line of the first plane, and to update values in the second set of registers with each read command for the selected word line of the second plane; and

    a state machine coupled to the external controller, the state machine is configured to;

    in response to each of the read commands for the selected word line of the first plane, read the updated values from the first set of registers, and provide read voltages on the selected word line in the first plane according to an order of the updated values in the first set of registers, andin response to each of the read commands for the selected word line of the second plane, read the updated values from the second set of registers, and provide read voltages on the selected word line in the second plane according to an order of the updated values in the second set of registers.

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