Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
First Claim
1. A method for providing a metallic interconnection layer of a semiconductor die, comprising:
- patterning and filling, using a two-dimension-capable multi-patterning process, alternating first and second sets of lines, the first set of lines and the second set of lines having first and second materials, respectively, the first and second materials having different etch characteristics;
patterning first self-aligned cuts for the first set of lines, the first self-aligned cuts having an overlay margin permitting the first self-aligned cuts to overlap one or more neighboring lines of the second set of lines;
selectively etching, due to the first and second materials having different etch characteristics, the first and second sets of lines and the first self-aligned cuts to remove the first set of lines other than portions of the first set of lines protected by the first self-aligned cuts but not the second set of lines and to provide first trenches at the first set of lines other than the portions of the first set of lines protected by the first self-aligned cuts;
filling the first trenches with a third material having different etch characteristics than the second material;
patterning second self-aligned cuts for the second set of lines, the second self-aligned cuts having an overlay margin permitting the second self-aligned cuts to overlap one or more neighboring trenches of the first trenches;
selectively etching, due to the second and third materials having different etch characteristics, the second set of lines, the first trenches, and the second self-aligned cuts to remove the second set of lines other than portions of the second set of lines protected by the second self-aligned cuts but not the first trenches and to provide second trenches at the second set of lines other than the portions of the second set of lines protected by the second self-aligned cuts;
filling the second trenches with a fourth material having different etch characteristics than the third material;
patterning first self-aligned vias for the first or second trenches with a relaxed overlay margin, the relaxed overlay margin permitting the first self-aligned vias to overlap one or more neighboring trenches of the first or second trenches;
selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide first via holes;
stripping fill materials in the first and second trenches to provide a stripped pattern; and
forming conductive lines and vias in the stripped pattern to provide the metallic interconnection layer for the semiconductor die.
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Accused Products
Abstract
Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.
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Citations
19 Claims
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1. A method for providing a metallic interconnection layer of a semiconductor die, comprising:
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patterning and filling, using a two-dimension-capable multi-patterning process, alternating first and second sets of lines, the first set of lines and the second set of lines having first and second materials, respectively, the first and second materials having different etch characteristics; patterning first self-aligned cuts for the first set of lines, the first self-aligned cuts having an overlay margin permitting the first self-aligned cuts to overlap one or more neighboring lines of the second set of lines; selectively etching, due to the first and second materials having different etch characteristics, the first and second sets of lines and the first self-aligned cuts to remove the first set of lines other than portions of the first set of lines protected by the first self-aligned cuts but not the second set of lines and to provide first trenches at the first set of lines other than the portions of the first set of lines protected by the first self-aligned cuts; filling the first trenches with a third material having different etch characteristics than the second material; patterning second self-aligned cuts for the second set of lines, the second self-aligned cuts having an overlay margin permitting the second self-aligned cuts to overlap one or more neighboring trenches of the first trenches; selectively etching, due to the second and third materials having different etch characteristics, the second set of lines, the first trenches, and the second self-aligned cuts to remove the second set of lines other than portions of the second set of lines protected by the second self-aligned cuts but not the first trenches and to provide second trenches at the second set of lines other than the portions of the second set of lines protected by the second self-aligned cuts; filling the second trenches with a fourth material having different etch characteristics than the third material; patterning first self-aligned vias for the first or second trenches with a relaxed overlay margin, the relaxed overlay margin permitting the first self-aligned vias to overlap one or more neighboring trenches of the first or second trenches; selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide first via holes; stripping fill materials in the first and second trenches to provide a stripped pattern; and forming conductive lines and vias in the stripped pattern to provide the metallic interconnection layer for the semiconductor die. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. One or more non-transitory computer-readable storage media having instructions stored thereon that, responsive to execution by one or more computer processors, performs operations comprising:
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patterning and filling, using a two-dimension-capable multi-patterning process, alternating first and second sets of lines, the first set of lines and the second set of lines having first and second materials, respectively, the first and second materials having different etch characteristics; patterning first self-aligned cuts for the first set of lines, the first self-aligned cuts having an overlay margin permitting the first self-aligned cuts to overlap one or more neighboring lines of the second set of lines; selectively etching, due to the first and second materials having different etch characteristics, the first and second sets of lines and the first self-aligned cuts to remove the first set of lines other than portions of the first set of lines protected by the first self-aligned cuts but not the second set of lines and to provide first trenches at the first set of lines other than the portions of the first set of lines protected by the first self-aligned cuts; filling the first trenches with a third material having different etch characteristics than the second material; patterning second self-aligned cuts for the second set of lines, the second self-aligned cuts having an overlay margin permitting the second self-aligned cuts to overlap one or more neighboring trenches of the first trenches; selectively etching, due to the second and third materials having different etch characteristics, the second set of lines, the first trenches, and the second self-aligned cuts to remove the second set of lines other than portions of the second set of lines protected by the second self-aligned cuts but not the first trenches and to provide second trenches at the second set of lines other than the portions of the second set of lines protected by the second self-aligned cuts; filling the second trenches with a fourth material having different etch characteristics than the third material; patterning first self-aligned vias for the first or second trenches with a relaxed overlay margin, the relaxed overlay margin permitting the first self-aligned vias to overlap one or more neighboring trenches of the first or second trenches; selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide first via holes; stripping fill materials in the first and second trenches to provide a stripped pattern; and forming conductive lines and vias in the stripped pattern to provide a metallic interconnection layer for a semiconductor die. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification