Semiconductor device arrangement and a method for forming a semiconductor device arrangement
First Claim
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1. A semiconductor device arrangement comprising:
- a semiconductor substrate comprising a semiconductor substrate front side and a semiconductor substrate back side, wherein the semiconductor substrate comprises at least one electrical element formed at the semiconductor substrate front side; and
a plurality of porous semiconductor regions formed at the semiconductor substrate back side,wherein a density of the porous semiconductor regions is less than a density of non-porous semiconductor material separating the porous semiconductor regions.
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Abstract
A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.
5 Citations
20 Claims
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1. A semiconductor device arrangement comprising:
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a semiconductor substrate comprising a semiconductor substrate front side and a semiconductor substrate back side, wherein the semiconductor substrate comprises at least one electrical element formed at the semiconductor substrate front side; and a plurality of porous semiconductor regions formed at the semiconductor substrate back side, wherein a density of the porous semiconductor regions is less than a density of non-porous semiconductor material separating the porous semiconductor regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 18, 19, 20)
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9. A method for forming a semiconductor device arrangement, the method comprising:
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thinning at least a portion of the semiconductor wafer to form a thinned wafer portion, wherein the thinned wafer portion extends over more than 50% of an area of the semiconductor wafer; and forming a plurality of porous semiconductor regions in the semiconductor wafer, wherein the semiconductor wafer comprises a support structure laterally surrounding the thinned wafer portion of the semiconductor wafer; and individualizing chip regions of the thinned wafer portion by separating the chip regions through the plurality of porous semiconductor regions, wherein the plurality of porous semiconductor regions are formed in kerf regions between the chip regions of the thinned wafer portion, or introducing a dopant into the thinned wafer portion via a back side of the thinned wafer portion to form a dopant region, wherein the plurality of porous semiconductor regions comprise a higher diffusion rate of dopants passing through the plurality of porous semiconductor regions than a surrounding semiconductor material of the thinned wafer portion while introducing the dopant, wherein the plurality of porous semiconductor regions are formed at a back side of the thinned wafer portion of the semiconductor wafer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for reducing thickness variations in a semiconductor substrate, the method comprising:
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detecting at least one thickness aberration region at a side of a semiconductor substrate; forming at least one porous semiconductor region in the at least one thickness aberration region; and selectively removing at least part of the at least one porous semiconductor region to at least partially remove the at least one thickness aberration region.
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Specification