Semiconductor wafer and method of backside probe testing through opening in film frame

• US 9,793,186 B1
• Filed: 08/08/2016
• Issued: 10/17/2017
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Seddon, Michael J., Lee, Heng Chen
• Primary Examiner(s): Nguyen, Tram H
• Application Number:
  US15/230,875
• Time in Patent Office: 435 Days
• Field of Search: 438381, 257 48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2865 Holding devices, e.g. chucks; Handlers or transport devices having contacts G01R31/2863
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Abstract

A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer;

providing a film frame including a tape portion with an opening through the tape portion;

mounting the semiconductor wafer over the opening in the tape portion of the film frame; and

probe testing the semiconductor wafer through the opening in the tape portion of the film frame.

2. The method of claim 1, wherein the opening is disposed in a center region of the tape portion of the film frame.

3. The method of claim 1, further including:

providing a wafer probe chuck including a raised surface; and

mounting the film frame to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the semiconductor wafer.

4. The method of claim 1, further including:

providing a plurality of openings through the tape portion of the film frame; and

probe testing of the semiconductor wafer through the openings in the tape portion of the film frame.

5. The method of claim 1, further including:

forming a conductive layer over a surface of the semiconductor wafer; and

probe testing the conductive layer through the opening in the tape portion of the film frame.

6. The method of claim 1, further including removing a portion of a base material of the semiconductor wafer to reduce a thickness of the semiconductor wafer.

7. A method of making a semiconductor device, comprising:

providing a carrier with an opening through the carrier;

mounting a semiconductor wafer over the opening in the carrier, wherein the opening is disposed in a center region of the carrier; and

probe testing the semiconductor wafer through the opening in the carrier.

9. The method of claim 7, further including:

providing a plurality of openings through the carrier; and

probe testing of the semiconductor wafer through the openings in the carrier.

10. The method of claim 7, further including:

forming a conductive layer over a surface of the semiconductor wafer; and

probe testing the conductive layer through the opening in the carrier.

11. The method of claim 7, further including removing a portion of a base material of the semiconductor wafer to reduce a thickness of the semiconductor wafer.

12. The method of claim 7, further including forming a conductive trace in or on the carrier.

8. A method of making a semiconductor device, comprising:

providing a carrier with an opening through the carrier;

mounting a semiconductor wafer over the opening in the carrier;

providing a wafer probe chuck including a raised surface;

mounting the carrier to the wafer probe chuck with the raised surface extending through the opening in the carrier to contact the semiconductor wafer; and

probe testing the semiconductor wafer through the opening in the carrier.

13. An apparatus for probe testing a semiconductor wafer, comprising:

a carrier with an opening through the carrier, wherein the opening is disposed in a center region of the carrier; and

a semiconductor wafer disposed over the opening in the carrier, wherein the semiconductor wafer is probe tested through the opening in the carrier.

14. The apparatus of claim 13, further including a wafer probe chuck including a raised surface, wherein the carrier is mounted to the wafer probe chuck with the raised surface extending through the opening in the carrier to contact the semiconductor wafer.

15. The apparatus of claim 13, further including a plurality of openings through the carrier, wherein the semiconductor wafer is probe tested through the openings in the carrier.

16. The apparatus of claim 13, further including a conductive layer over a surface of the semiconductor wafer, wherein the conductive layer is probe tested through the opening in the carrier.

17. The apparatus of claim 13, wherein a thickness of the semiconductor wafer is less than 75 micrometers.

18. The apparatus of claim 13, further including a conductive trace formed in or on the carrier.