Formation of through via before contact processing

• US 9,793,192 B2
• Filed: 12/07/2015
• Issued: 10/17/2017
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Primary Examiner(s): Anya, Igwe U
• Application Number:
  US14/961,293
• Publication Number:
  US 20160099196A1
• Time in Patent Office: 680 Days
• Field of Search: 257621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

Claims

1. A stacked integrated circuit (IC) comprising:

a first semiconductor die having a front-side and a back-side, wherein said first semiconductor die contains a substrate and one or more active devices on the substrate;

one or more through silicon vias (TSVs) running through the substrate and a front-side insulation layer of said first semiconductor die;

an inter-layer dielectric (ILD) layer on said front-side of said first semiconductor die, said ILD layer having at least one contact physically connected to a front-side of said one or more TSVs and an interface between said at least one contact and said one or more TSVs, wherein one of the at least one contact comprises a first contact and a second contact, wherein the first contact and the second contact have widths that are smaller than a width of the said one or more TSVs, wherein the interface comprises a redistribution layer;

an inter-metal dielectric (IMD) layer on said ILD layer, said IMD layer having at least one bonding pad electrically connected to said at least one contact;

a second semiconductor die connected to said first semiconductor die at said at least one bonding pad; and

a metallization layer on said back-side of said first semiconductor die, wherein said metallization layer comprises;

at least one back-side dielectric layer over said back-side; and

an etch-stop layer over one of said at least one back-side dielectric layers;

said metallization layer having at least one back-side contact having a first side electrically connected to a back-side of said one or more TSVs and a second side opposite the first side exposed to allow current to flow through the second side.

2. The stacked IC of claim 1, wherein the ILD layer is in direct contact with a portion of the front-side of said one or more TSVs.

3. The stacked IC of claim 1, further comprising a conductive material extending through the ILD layer to contact the substrate.

4. The stacked IC of claim 3, wherein the conductive material is in electrical connection with at least one of the one or more active devices on the substrate.

5. The stacked IC of claim 1, further comprising a liner oxide disposed along sidewalls of the one or more TSVs.

6. The stacked IC of claim 1, wherein the redistribution layer comprises more than one metal layer.

7. A semiconductor device comprising:

a semiconductor substrate with active devices located on a first side of the semiconductor substrate;

a through substrate via extending from the first side of the semiconductor substrate to a second side of the semiconductor substrate, the second side of the semiconductor substrate being opposite the first side of the semiconductor substrate;

a plurality of first contacts over the first side of the semiconductor substrate and in electrical connection with the through substrate via, wherein each one of the plurality of first contacts has a width that is less than a width of the through substrate via, wherein the plurality of first contacts over the first side of the semiconductor substrate are in electrical connection with the through substrate via through a redistribution layer;

a bond pad over the first side of the semiconductor substrate and electrically connected to the plurality of first contacts, wherein a first surface of the bond pad is exposed for electrical contact; and

a second contact located adjacent to the second side of the semiconductor substrate and electrically connected to the through substrate via, wherein a second surface of the second contact is exposed for electrical contact.

8. The semiconductor device of claim 7, wherein the plurality of first contacts are embedded within a first dielectric layer which also surrounds at least a portion of the through substrate via.

9. The semiconductor device of claim 8, further comprising a contact extending through the first dielectric layer and in electrical contact with the semiconductor substrate.

10. The semiconductor device of claim 8, wherein the first dielectric layer is in physical contact with a conductive surface of the through substrate via.

11. The semiconductor device of claim 10, further comprising a second semiconductor die bonded to the bond pad.

12. The semiconductor device of claim 11, wherein the second semiconductor die comprises a through substrate via that extends from a first side of a second semiconductor substrate to a second side of the semiconductor substrate.

13. The semiconductor device of claim 7, further comprising a liner oxide disposed along sidewalls of the through substrate via.

14. The semiconductor device of claim 7, wherein the redistribution layer comprises a plurality of metal layers.

15. A semiconductor device comprising:

a first semiconductor die comprising;

a first semiconductor substrate;

a first through substrate via extending from a first side of the first semiconductor substrate to a second side of the first semiconductor substrate, the first through substrate via having a first width;

a first contact in connection with the first through substrate via, the first contact having a second width less than the first width;

a second contact in connection with the first through substrate via, the second contact having a second width less than the first width;

a first bond pad in electrical connection with both the first contact and the second contact; and

a dielectric layer, wherein each of the first through substrate via, the first contact, and the second contact extend at least partially into the dielectric layer; and

a second semiconductor die bonded to the first semiconductor die, wherein the second semiconductor die further comprises;

a second semiconductor substrate;

a second bond pad bonded to the first bond pad; and

a second through substrate via extending from a first side of the second semiconductor substrate to a second side of the second semiconductor substrate, wherein the second through substrate via is in electrical connection with the second bond pad.

16. The semiconductor device of claim 15, wherein the first contact is in direct physical connection with the first through substrate via.

17. The semiconductor device of claim 16, wherein the second contact is in direct physical connection with the first through substrate via.

18. The semiconductor device of claim 15, wherein the dielectric layer is in physical contact with a conductive surface of the first through substrate via.

19. The semiconductor device of claim 15, wherein the first contact is in connection with the first through substrate via through a redistribution layer.

20. The semiconductor device of claim 19, wherein the redistribution layer comprises more than one metal layer.