Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask

• US 9,793,204 B2
• Filed: 03/09/2016
• Issued: 10/17/2017
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Hung, Huang, Chun-Hsien, Chen, I-Tseng
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US15/065,800
• Publication Number:
  US 20170141028A1
• Time in Patent Office: 587 Days
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

Claims

1. A method for manufacturing a semiconductor structure comprising:

forming a dielectric layer on a conductive structure, wherein the forming the dielectric layer comprises;

forming a first portion of the dielectric layer to conceal the conductive structure;

removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure; and

forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;

forming a metal hard mask on the dielectric layer without performing a degas process;

patterning the metal hard mask; and

patterning the dielectric layer with the patterned metal hard mask to form a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer and a second through hole extending merely through the second portion of the dielectric layer.

2. The method of claim 1,

wherein the second through hole exposes the conductive structure.

3. The method of claim 1, wherein the patterning the metal hard mask comprises:

forming a photoresist on the metal hard mask;

patterning the photoresist; and

patterning the metal hard mask with the patterned photoresist.

4. The method of claim 3, wherein the patterning the metal hard mask further comprises:

forming a bottom layer and a middle layer between the photoresist and the metal hard mask.

5. The method of claim 1, wherein the metal hard mask is made of titanium nitride, tantalum nitride, boron nitride, titanium, tantalum, or combinations thereof.

6. The method of claim 1, wherein the metal hard mask is formed by PVD or CVD.

7. The method of claim 1, further comprising:

forming at least one conductive feature in the second through hole to be connected to the conductive structure.

8. The method of claim 1, wherein the conductive structure is a transistor.

9. The method of claim 1, wherein an initial temperature of the dielectric layer for forming the metal hard mask is about 15°

C. to about 30°

C.

10. The method of claim 1, wherein a material composition of the first portion of the dielectric layer is different than a material composition of the second portion of the dielectric layer.

11. The method of claim 1, wherein the forming the metal hard mask comprises:

forming the metal hard mask directly on the second portion of the dielectric layer such that the metal hard mask contacts a top surface of the second portion of the dielectric layer.

12. The method of claim 1, wherein the first through hole exposes a silicide contact underlying the first portion of the dielectric layer.

13. The method of claim 1, wherein the forming the metal hard mask comprises:

forming the metal hard mask directly on the dielectric layer.

14. A method for manufacturing a semiconductor structure comprising:

forming a first portion of a dielectric layer to conceal a conductive structure;

removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure;

forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;

forming a metal hard mask directly on the dielectric layer without performing a degas process between the forming the second portion of the dielectric layer and the forming the metal hard mask;

patterning the metal hard mask;

patterning the first portion of the dielectric layer and the second portion of the dielectric layer to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and

patterning the second portion of the dielectric layer to define a second through hole extending through the second portion of the dielectric layer.

15. The method of claim 14, wherein the top surface of the conductive structure is re-exposed through the second through hole.

20. The method of claim 14, wherein an initial temperature of the dielectric layer for forming the metal hard mask is less than 30°

C.

16. A method for manufacturing a semiconductor structure comprising:

forming a dielectric layer on a conductive structure, wherein the forming the dielectric layer comprises;

forming a first portion of the dielectric layer to conceal the conductive structure;

removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure; and

forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;

-and

forming a metal hard mask on the dielectric layer without performing a degas process between the forming the dielectric layer and the forming the metal hard mask to provide that, at an initialization of the forming the metal hard mask, the dielectric layer has a temperature of less than about 30°

C.;

patterning the metal hard mask; and

patterning the dielectric layer with the patterned metal hard mask to form a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer and a second through hole extending merely through the second portion of the dielectric layer.

17. The method of claim 16, wherein the second through hole exposes the conductive structure.

18. The method of claim 16, wherein the first through hole exposes a silicide contact underlying the first portion of the dielectric layer.

19. The method of claim 16, wherein a material composition of the first portion of the dielectric layer is different than a material composition of the second portion of the dielectric layer.