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Method of maintaining the state of semiconductor memory having electrically floating body transistor

  • US 9,793,277 B2
  • Filed: 04/11/2017
  • Issued: 10/17/2017
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising;

    said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

    a first bipolar device having a first floating base region, a first emitter, and a first collector; and

    a second bipolar device having a second floating base region, a second emitter, and a second collector;

    wherein said first floating base region is common to said second floating base region,wherein said first collector is common to said second collector,wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors,wherein said first and second collectors are commonly connected to at least two of said memory cells; and

    a control circuit configured to provide electrical signals to said first and second collectors.

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