Power MOSFET semiconductor

• US 9,793,391 B2
• Filed: 11/09/2015
• Issued: 10/17/2017
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Haeberlen, Oliver, Krumrey, Joachim, Hirler, Franz, Rieger, Walter
• Primary Examiner(s): Fan, Bo
• Application Number:
  US14/935,877
• Publication Number:
  US 20160233331A1
• Time in Patent Office: 708 Days
• Field of Search: 257330, 257172, 257288, 438270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first trench and a second trench in the semiconductor substrate;

forming a first oxide layer covering at least a lower portion of side walls of the first trench and a lower portion of side walls of the second trench;

forming a conductive region at least in the lower portion of the first trench and at least in the lower portion of the second trench, comprising depositing a conductive material and back-etching the conductive material so that a larger portion of the deposited conductive material is removed during back-etching in the first trench compared to the second trench;

forming via thermal oxidation a first insulating region on upper portions of the side walls of the first trench and a second insulating region on upper portions of the side walls of the second trench not covered with the first oxide layer;

forming a first gate electrode in the upper portion of the first trench and a second gate electrode in the upper portion of the second trench;

forming source regions of the first conductivity type and a body region of a second conductivity type adjacent to the source regions; and

forming a source metallization in electrical contact to the source regions and the second gate electrode;

wherein the back-etching is performed such that the conductive region in the first vertical trench has, in a vertical direction perpendicular to a bottom wall of the first vertical trench, a first vertical extension; and

that the conductive region in the second vertical trench has, in the vertical direction, a second vertical extension larger than the first vertical extension.

2. The method of claim 1, wherein the first insulating region and the second insulating region are formed such that a capacitance per unit area between the second gate electrode and the body region is higher than a capacitance per unit area between the first gate electrode and the body region.

3. The method of claim 1, wherein the first insulating region and the second insulating region are formed such that a thickness of the second insulating region between the second gate electrode and the body region is smaller than a thickness of the first insulating region between the first gate electrode and the body region.

4. The method of claim 1, wherein the conductive material is poly-Silicon.

5. The method of claim 1, prior to performing the second thermal oxidation process comprising:

masking the first trench; and

subsequently

performing an etching process to expose the upper portion of the second trench.

6. The method of claim 1, prior to performing the first thermal oxidation process comprising:

masking the second trench; and

subsequently

performing an etching process to expose the upper portion of the first trench.