MOSFET device and fabrication

• US 9,793,393 B2
• Filed: 09/23/2013
• Issued: 10/17/2017
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Lee, Il Kwan, Chang, Hong, Li, Wenjun, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US14/033,692
• Publication Number:
  US 20140091386A1
• Time in Patent Office: 1,485 Days
• Field of Search: None
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.

Claims

1. A semiconductor device, comprising:

a substrate;

an active gate trench in the substrate;

a source polysilicon pickup trench in the substrate;

a polysilicon electrode disposed in the source polysilicon pickup trench;

a body region in the substrate; and

an insulating spacer that is adjacent to a top portion of the source polysilicon pickup trench, that extends above the polysilicon electrode disposed in the source polysilicon pickup trench, that allows the source polysilicon pickup trench to be formed by self-aligned etching, that is at least in part in contact with the body region, and that separates the body region from a sidewall of the source polysilicon pickup trench;

wherein;

a top side of the polysilicon electrode is below a bottom of the body region.

2. The semiconductor device of claim 1, further comprising a contact hole filled with a metal conductor extending from the polysilicon electrode to a source metal layer deposited on a top side of the semiconductor device.

3. The semiconductor device of claim 2, wherein the contact hole is narrower in width than the polysilicon electrode.

4. The semiconductor device of claim 2, wherein the metal conductor and the source metal layer are formed using different types of metals.

5. The semiconductor device of claim 1, wherein the source polysilicon pickup trench is deeper than the active gate trench.

6. The semiconductor device of claim 1, wherein the source polysilicon pickup trench is narrower than the active gate trench.

7. The semiconductor device of claim 1, wherein the insulating spacer does not extend beyond a bottom side of the polysilicon electrode.

8. The semiconductor device of claim 1, wherein the insulating spacer is located outside the source polysilicon pickup trench.

9. A method of fabricating a semiconductor device, comprising:

forming an insulating spacer;

forming an active gate trench and a source polysilicon pickup trench in a substrate, including performing self-aligned etching using at least the insulating spacer to form the source polysilicon pickup trench, wherein the insulating spacer is adjacent to a top portion of the source polysilicon pickup trench;

forming an active gate electrode in the active gate trench and a polysilicon electrode in the source polysilicon pickup trench, wherein the insulating spacer is adjacent to a top portion of the source polysilicon pickup trench and extends above the polysilicon electrode in the source polysilicon pickup trench; and

implanting a body region;

wherein;

the polysilicon electrode has a top side that is below a bottom of the body region; and

the insulating spacer and the body region are formed in such a way that the insulating spacer is at least in part in contact with the body region and the insulating spacer separates the body region from a side wall of the source polysilicon pickup trench.

10. The method of claim 9, further comprising:

forming a contact hole above the a polysilicon electrode;

filling the contact hole with a metal conductor;

depositing a source metal layer on a top side of the semiconductor device;

the metal conductor extending from the polysilicon electrode to a source metal layer deposited on top side of semiconductor device.

11. The method of claim 10, wherein the contact hole is formed to be narrower in width than the polysilicon electrode.

12. The method of claim 10, wherein the metal conductor and the source metal layer are formed using different types of metals.

13. The method of claim 9, wherein the source polysilicon pickup trench is formed to be deeper than the active gate trench.

14. The method of claim 9, wherein the source polysilicon pickup trench is formed to be narrower than the active gate trench.

15. The method of claim 9, wherein the insulating spacer used to form the source polysilicon pickup trench does not extend beyond a bottom side of the polysilicon electrode.

16. The method of claim 9, wherein the insulating spacer used to form the source polysilicon pickup trench is located outside the source polysilicon pickup trench.