Vertical vacuum channel transistor

• US 9,793,395 B1
• Filed: 10/06/2016
• Issued: 10/17/2017
• Est. Priority Date: 10/06/2016
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Liu, Qing, Xie, Ruilong, Yeh, Chun-chen
• Primary Examiner(s): Bradley, Stephen
• Application Number:
  US15/287,134
• Time in Patent Office: 376 Days
• CPC Class Codes: H01L 21/02614 Transformation of metal, e.g. oxidation, nitridation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

Claims

1. A method of fabricating features of a vertical transistor, the method comprising:

forming a fin in a substrate comprising a semiconductor material;

oxidizing a portion of the semiconductor material of the fin such that an oxidized portion is arranged between a source and a drain;

forming a gate stack on one side of the fin;

removing the oxidized portion of the fin to form a vacuum channel opening, the vacuum channel opening contacting the gate stack; and

performing a directional deposition process to deposit a dielectric on another side of the fin such that the vacuum channel opening remains open.

2. The method of claim 1, wherein the directional deposition process comprises gas cluster ion beam.

3. The method of claim 1, wherein the dielectric is silicon nitride.

4. The method of claim 1, further comprising doping the semiconductor material of the substrate with a dopant before forming the fin.

5. The method of claim 4, wherein the fin is arranged on a doped region forming a source, and another doped region above the vacuum channel opening forms a drain.

6. The method of claim 1, wherein the oxidizing is performed by annealing.