Fabrication of a strained region on a substrate

• US 9,793,398 B1
• Filed: 08/02/2016
• Issued: 10/17/2017
• Est. Priority Date: 08/02/2016
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lauer, Isaac, Liu, Jiaxing, Mo, Renee T.
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon
• Application Number:
  US15/226,834
• Time in Patent Office: 441 Days
• Field of Search: 257213, 438142
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02428 Structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H05K 999/99 dummy group

Abstract

A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Claims

1. A method of forming a strained channel for a field effect transistor, comprising:

forming a sacrificial layer on a substrate;

forming a channel layer on the sacrificial layer;

forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer;

forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs; and

removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

2. The method of claim 1, wherein the sacrificial layer is silicon-germanium (SiGe).

3. The method of claim 1, wherein the stressor layer is silicon nitride (SiN).

4. The method of claim 1, wherein the substrate surface has a single crystal structure, and the sacrificial layer is a single crystal layer formed on the substrate surface by a heteroepitaxial growth process.

5. The method of claim 1, wherein the channel layer is a single crystal silicon formed on the sacrificial layer by a heteroepitaxial growth process.

6. The method of claim 1, wherein the selective etch uses gaseous hydrogen chloride (HCl).

7. The method of claim 1, wherein the channel layer has a thickness in the range of about 5 nm to about 100 nm, and the stressor layer is at least as thick as the channel layer.

8. The method of claim 1, wherein the sacrificial layer has a thickness in the range of about 10 nm to about 100 nm.

9. The method of claim 1, further comprising heat treating the channel blocks and substrate to chemically bond the channel blocks to the substrate surface.

10. The method of claim 9, wherein the heat treating is conducted at a temperature in the range of about 300°

C. to about 750°

C. for a duration in the range of about 1 hour to about 18 hours.

11. A method of forming a strained channel, comprising:

forming a single crystal silicon-germanium sacrificial layer on a single crystal substrate surface;

forming a single crystal silicon channel layer on the single crystal silicon-germanium sacrificial layer;

forming a silicon nitride stressor layer on the single crystal silicon channel layer, wherein the silicon nitride stressor layer has a tensile or compressive stress;

forming at least one etching trench by removing at least a portion of the silicon nitride stressor layer, single crystal silicon channel layer, and single crystal silicon-germanium sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the single crystal silicon-germanium sacrificial layer, and separates the silicon nitride stressor layer, single crystal silicon channel layer, and single crystal silicon-germanium sacrificial layer into two or more silicon nitride stressor islands, single crystal silicon channel blocks, and single crystal silicon-germanium sacrificial slabs; and

removing the single crystal silicon-germanium sacrificial slabs to release the single crystal silicon channel blocks from the substrate using a selective etch, wherein the single crystal silicon channel blocks adhere to the single crystal substrate surface.

12. The method of claim 11, wherein the single crystal silicon channel layer has a thickness in the range of about 5 nm to about 100 nm, and the silicon nitride stressor layer has a thickness in the range of about 5 nm to about 100 nm, where the stressor layer is at least as thick as the channel layer.

13. The method of claim 11, wherein the etching trench has a width equal to or greater than the thickness of the silicon-germanium sacrificial layer.

14. The method of claim 11, wherein the single crystal substrate surface is a <

100>

surface of a single crystal silicon substrate.

15. The method of claim 11, wherein the selective etch uses a solution made of a hydrofluoric acid (HF) solution, a hydrogen peroxide (H₂O₂) solution, and acetic acid (CH₃COOH).

16. An intermediate channel structure, comprising;

a substrate with a single crystal surface;

one or more silicon-germanium pillars, wherein each of the one or more silicon-germanium pillars supports a silicon channel block, and wherein the silicon channel block has a width in the range of about 250 nm to about 10 μ

m, and a length in the range of about 2 μ

m to about 100 μ

m; and

a silicon nitride stressor island on each silicon channel block, wherein the stressor island applies a stress to a top surface of the silicon channel block.

17. The intermediate device structure of claim 16, wherein the stressor island applies a tensile stress to a top surface of the silicon channel block in the range of about +1.6 GPa to about −

3 GPa.

18. The intermediate device structure of claim 16, wherein the substrate is a single crystal silicon wafer.

19. The intermediate device structure of claim 18, wherein the silicon channel blocks are separated by an etching trench have a width in the range of about 10 nm to about 150 nm, where the width of the etching trench is equal to or greater than the thickness of the silicon-germanium pillars.