Vertical field effect transistor including extension and stressors

• US 9,793,401 B1
• Filed: 05/25/2016
• Issued: 10/17/2017
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Karthik, Cheng, Kangguo, Hashemi, Pouya, Reznicek, Alexander
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US15/164,046
• Time in Patent Office: 510 Days
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A vertical field effect transistor (FET) includes a first source/drain region formed on an upper surface of a semiconductor substrate, and a semiconductor channel material that extends vertically from the first source/drain region to a second source/drain region. A metal gate structure encapsulating the semiconductor channel material. The vertical FET further includes a stressor region that contacts the semiconductor channel material and the first source/drain region. The combination of the semiconductor channel material and the stressor region defines a total length of a strained channel region of the vertical field effect transistor.

Claims

1. A method of inducing strain on a channel region of a vertical transistor, the method comprising:

forming a channel region that extends from a first source/drain region to a second source/drain region;

encapsulating a first portion of the channel region with a first encapsulating structure and a second portion of the channel region with a second encapsulating structure;

removing the second encapsulating structure while maintaining the first encapsulating structure to expose the second portion of the channel region; and

replacing the second portion of the channel region with a stressor region that induces a strain on the first portion of the channel region.

2. The method of claim 1, wherein the first encapsulating structure is a metal gate structure and the second encapsulating structure is an inter-layer dielectric (ILD) material, and wherein removing the second encapsulating structure includes selectively etching the second encapsulating structure while maintaining the second portion of the channel region.

3. The method of claim 1, wherein replacing the second portion of the channel region includes:

selectively etching the second portion of the channel region, the second portion extending from first source/drain region to the first portion of the channel region;

performing a sigma etching process that forms a first v-shaped groove in the first source/drain region and a second v-shaped groove in the first channel region; and

forming the stressor region having a first end that contacts the first source/drain region and a second end that contacts the first portion of the channel region.

4. The method of claim 3, wherein a width of the channel region controls a depth of the first and second v-shaped grooves self-terminates.

5. The method of claim 3, wherein forming the stressor region includes epitaxially growing a doped semiconductor material from the first source/drain region exposed by the first v-shaped groove and from the first portion of the channel region exposed by the second v-shaped groove, the doped semiconductor material having a lattice constant that is different from a lattice constant of the first portion of the channel region.

6. The method of claim 3, wherein forming the stressor region includes:

performing an atomic layer deposition process so as to deposit a doped semiconductor material extending from the first source/drain region exposed by the first v-shaped groove to the first portion of the channel region exposed by the second v-shaped groove; and

performing an anneal process so as to activate dopants in the semiconductor material such that a lattice constant of the stressor region is different from a lattice constant of the first channel portion.

7. The method of claim 5, wherein the first portion of the channel region comprises silicon (Si) and the doped semiconductor material of the stressor region comprises silicon germanium (SiGe) so as to induce a compressive strain on the channel region.

8. The method of claim 5, wherein the first portion of the channel region comprises silicon (Si) and the doped semiconductor material of the stressor region comprises carbon doped silicon (Si:

C) so as to induce a tensile strain on the channel region.

10. The method of claim 8, wherein the encapsulating structure is a metal gate structure, and wherein selectively removing the first portion of the channel region includes performing a sigma etch to form a first v-shaped groove that extends into the preserved second portion of the channel region.

9. A method of inducing a strain on a channel region of a vertical field effect transistor (FET), the method comprising:

removing an encapsulating structure to form a void that exposes a first portion of the channel region, the channel region having a first lattice constant;

selectively removing the first portion of the channel region while preserving a second portion of the channel region, the second portion having a first channel end connected to a first source/drain region and a second channel end exposed to the void; and

forming a stressor region having a first stressor end formed against the second channel and a second stressor end formed against a second source/drain region, the stressor region having a second lattice constant different from the first lattice constant so as to induce a strain on the preserved second portion of the channel region.

11. The method of claim 9, wherein a width of the channel region controls a depth of the first and second v-shaped grooves self-terminates.

12. The method of claim 9, wherein forming the stressor region includes epitaxially growing a doped semiconductor material from the preserved second portion exposed by the v-shaped groove.

13. The method of claim 9, wherein forming the stressor region includes performing an atomic layer deposition process to deposit a doped semiconductor material in the first v-shaped groove so as to contact the preserved second portion of the channel region;

and

performing a thermal anneal process so as to activate the doped semiconductor material.

14. The method of claim 9, wherein the preserved second portion of the channel region comprises silicon (Si) and the doped semiconductor material of the stressor region comprises silicon germanium (SiGe) so as to induce a compressive strain on the channel region.

15. The method of claim 9, wherein the preserved second portion of the channel region comprises silicon (Si) and the doped semiconductor material of the stressor region comprises carbon doped silicon (Si:

C) so as to induce a tensile strain on the channel region.