Power factor correction circuit and power supply device

• US 9,793,793 B2
• Filed: 06/09/2016
• Issued: 10/17/2017
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kataoka, Kohtaroh, Nomura, Masaru, Wakaiki, Shuji, Igarashi, Hiroki, Shibata, Akihide, Iwata, Hiroshi, Shiomi, Takeshi
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): NASH, GARY A
• Application Number:
  US15/177,543
• Publication Number:
  US 20160380531A1
• Time in Patent Office: 495 Days
• Field of Search: 363 59- 62
• CPC Class Codes: H02M 1/0085 Partially controlled bridges
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 1/4233 using a bridge converter comprising active switches
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A power factor correction circuit includes: a coil and MOSFETs that boost an input voltage to generate a boosted voltage; a first capacitor having one end connected to a first output terminal, and the other end connected to an intermediate node; and a second capacitor having one end connected to the intermediate node, and the other end connected to a second output terminal. In a first operation mode, the boosted vol tage is applied to the two ends of the first capacitor when a positive voltage is input, and applied to the two ends of the second capacitor when a negative voltage is input. In a second operation mode, the boosted voltage is applied to two ends of the first and second capacitors connected in series. Thus, there is provided a power factor correction circuit which has a high efficiency and is compatible with an input voltage in a broad range.

Claims

1. A power factor correction circuit capable of switching an operation mode, the circuit comprising:

first and second input terminals for inputting an input voltage;

first and second output terminals;

a coil;

a switch circuit that, boosts the input voltage to generate a boosted voltage in cooperation with the coil;

a first capacitor having one end connected to the first output terminal, and the other end connected to an intermediate node; and

a second capacitor having one end connected, to the intermediate node, and the other end connected to the second output terminal, wherein

when a potential at the first input terminal is higher than a potential at the second input terminal in a first operation mode, the boosted voltage is applied to the two ends of the first capacitor such that a potential at the one end is higher than a potential at the other end,

when the potential at the first input terminal is lower than the potential at the second input terminal in the first operation mode, the boosted voltage is applied to the two ends of the second capacitor such that a potential at the one end is higher than a potential at the other end, and

in a second operation mode, the boosted voltage is applied to two ends of the first and second capacitors connected in series such that the potential at the one end of the first capacitor is higher than the potential at the other end of the second capacitor.

2. The power factor correction circuit according to claim 1, wherein

the switch circuit is a bidirectional switch including

a first transistor connected between a first node and a connection node, and

a second transistor connected between the connection node and a second node,

the power factor correction circuit further comprises:

a mode switching circuit having one end connected to the second node, and the other end connected to the intermediate node, the circuit being brought into an on-state in the first operation mode and into an off-state in the second operation mode;

a first rectifier element connected between the first node and the one end of the first capacitor so as to allow a current to flow from a first node side;

a second rectifier element connected between the first node and the other end of the second capacitor so as to allow a current to flow to the first node side;

a third rectifier element connected between the second node and the one end of the first capacitor so as to allow a current to flow from a second node side; and

a fourth rectifier element connected between the second node and the other end of the second capacitor so as to allow a current to flow to the second node side, and

the coil is connected at least one of between the first input terminal and the first node, and between the second input terminal and the second node.

3. The power factor correction circuit according to claim 2, wherein

the first transistor is a MOSFET or a HEMT having a first conduction terminal connected to the first node, and a second conduction terminal connected to the connection node,

the second transistor is a MOSFET or a HEMT having a second conduction terminal connected to the connection node, and a first conduction terminal connected to the second node,

the first conduction terminal is one of a source terminal and a drain terminal, and

the second conduction terminal is the other of the source terminal and the drain terminal.

4. The power factor correction circuit according to claim. 2, wherein

the first transistor is an IGBT or a bipolar transistor having a first conduction terminal connected to the first node, and a second, conduction terminal connected to the connection node,

the second transistor is an IGBT or a bipolar transistor having a second conduction terminal connected to the connection node, and a first conduction terminal connected to the second node,

the first conduction terminal is one of an emitter terminal and a collector terminal, and

the second conduction terminal is the other of the emitter terminal and the collector terminal.

5. The power factor correction circuit according to claim. 2, wherein

the third rectifier element is a MOSFET having a drain terminal connected to the one end of the first capacitor, and a source terminal connected to the second node, and

the fourth rectifier element is a MOSFET having a drain terminal connected to the second node, and a source terminal connected to the other end of the second capacitor.

6. The power factor correction circuit according to claim 2, further comprising:

a third capacitor connected in parallel with the third rectifier element between the second node and the one end of the first capacitor; and

a fourth capacitor connected in parallel with the fourth rectifier element between the second node and the other end of the second capacitor, wherein

a wiring route from the first node to the second node via the third capacitor is shorter than a wiring route from the first node to the second node via the third rectifier element, and

a wiring route from the second node to the first node via the fourth capacitor is shorter than a wiring route from the second node to the first node via the fourth rectifier element.

7. The power factor correction circuit according to claim 2, wherein

the mode switching circuit is a bidirectional switch that includes first and second MOSFETs having first conduction terminals connected to each other,

a second conduction terminal of the first MOSFET is connected to the second node,

a second conduction terminal of the second MOSFET is connected to the intermediate node,

the first conduction terminal is one of a source terminal and a drain terminal, and

the second conduction terminal is the other of the source terminal and the drain terminal.

8. The power factor correction circuit according to claim. 1, wherein

the switch circuit includes

a first transistor connected between a first node and a second node, and

a second transistor connected between the second node and a third, node,

the power factor correction circuit further comprises:

a mode switching circuit having one end connected to the second node, and the other end connected to the intermediate node, the circuit being brought into an on-state in the first operation mode and into an off-state in the second operation mode;

a first rectifier element connected between the first node and the one end of the first capacitor so as to allow a current to flow from a first node side;

a second rectifier element connected between the third node and the other end of the second, capacitor so as to allow a current to flow to a third node side;

a third rectifier element connected between the first node and a fourth node so as to allow a current to flow to the first node side; and

a fourth rectifier element connected between the third node and the fourth node so as to allow a current to flow from the third node side, and

the coil is connected at least one of between the second input terminal and the second node, and between the first input terminal and the fourth node.

9. The power factor correction circuit according to claim 8, wherein

the first transistor is a MOSFET or a HEMT having a drain terminal connected to the first node, and a source terminal connected to the second node, and

the second transistor is a MOSFET or a HEMT having a drain terminal connected to the second node, and a source terminal connected to the third node.

10. The power factor correction circuit according to claim 8, wherein

the first transistor is an IGBT or a bipolar transistor having a collector terminal connected to the first node, and an emitter terminal connected to the second node, and

the second transistor is an IGBT or a bipolar transistor having a collector terminal connected to the second node, and an emitter terminal connected to the third node.

11. The power factor correction circuit according to claim. 1, further comprising a control circuit that switches the operation mode to the first operation mode when the input voltage is lower than a first, threshold, and switches the operation mode to the second operation mode when the input voltage is higher than a second threshold.

12. A power supply device comprising:

the power factor correction circuit according to claim. 1; and

a DC-DC converter.

13. A power factor correction circuit comprising:

first and second input terminals;

first and second output terminals;

a coil;

a bidirectional switch that includes first and second transistors connected in anti-series, the bidirectional switch having one end connected to a first node, and the other end connected to a second node;

a first capacitor having one end connected to the first output terminal, and the other end connected to the second node;

a second capacitor having one end connected to the second node, and the other end connected to the second output terminal;

a first rectifier element connected between the first node and the one end of the first capacitor so as to allow a current to flow from a first node side; and

a second rectifier element connected between the first node and the other end of the second capacitor so as to allow a current to flow to the first node side, wherein

the power factor correction circuit has a current path between the first and second input terminals via the coil and the bidirectional switch, and

the coil is connected, at least one of between the first input terminal and the first node, and between the second node and the second, input terminal.

14. The power factor correction circuit according to claim 13, wherein

the first transistor is a MOSFET or a HEMT having a first conduction terminal, and a second conduction terminal connected to the second node,

the second transistor is a MOSFET or a HEMT having a first conduction terminal connected to the first conduction terminal of the first transistor, and a second conduction terminal connected to the first node,

the first conduction terminal is one of a drain terminal and a source terminal, and

the second conduction terminal is the other of the drain terminal and the source terminal.

15. The power factor correction circuit according to claim 13, wherein

the first transistor is an IGBT or a bipolar transistor having a first conduction terminal, and a second conduction terminal connected to the second node,

the second transistor is an IGBT or a bipolar transistor having a first conduction terminal connected to the first conduction terminal of the first transistor, and a second conduction terminal connected to the first node,

the first conduction terminal is one of a collector terminal and an emitter terminal, and

the second conduction terminal is the other of the collector terminal and the emitter terminal.

16. The power factor correction circuit according to claim 13, wherein

the first transistor is switched when a potential at the first input terminal is higher than a potential at the second input terminal, and

the second transistor is switched when the potential at the first input terminal is lower than the potential at the second input terminal.

17. The power factor correction circuit according to claim 16, wherein

the second transistor is controlled to an on-state when the potential at the first input terminal is higher than the potential at the second input terminal, and

the first transistor is controlled to an on-state when the potential at the first input terminal is lower than the potential at the second input terminal.

18. The power factor correction circuit according to claim 13, wherein the bidirectional switch further includes rectifier elements connected in anti-parallel with the first and second transistors.

19. A power supply device comprising:

the power factor correction circuit according to claim 13; and

a DC-DC converter.

20. A power factor correction circuit comprising:

first and second input terminals;

first and second output terminals;

a coil;

a first bidirectional switch that includes first and second transistors connected in anti-series, the first bidirectional switch having one end connected to a first node, and the other end connected to a second node;

a first capacitor having one end connected to the first output terminal, and the other end connected to a third node;

a second capacitor having one end connected to the third node, and the other end connected to the second output terminal;

a second bidirectional switch connected between the second node and the third node;

a first rectifier element connected between the first node and the one end of the first capacitor so as to allow a current to flow from, a first node side;

a second, rectifier element connected between, the first node and the other end of the second capacitor so as to allow a current to flow to the first node side;

a third rectifier element connected between the second node and the one end of the first capacitor so as to allow a current to flow from a second node side; and

a fourth rectifier element connected between the second node and the other end of the second capacitor so as to allow a current to flow to the second node side, wherein

the power factor correction circuit has a current path between the first and second input terminals via the coil and the first bidirectional switch, and

the coil is connected at least one of between the first input terminal and the first node, and between, the second node and the second input terminal.