System and method for reducing power loss in switched-capacitor power converters

• US 9,793,794 B2
• Filed: 02/04/2015
• Issued: 10/17/2017
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: The Trustees of Dartmounth College (Dartmouth College)
• Original Assignee: The Trustees of Dartmounth College (Dartmouth College)
• Inventors: Stauth, Jason T., Kesarwani, Kapil
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US15/116,780
• Publication Number:
  US 20160352218A1
• Time in Patent Office: 986 Days
• Field of Search: 327148, 327157, 327530, 327534-543, 327546, 327365-508, 363 59, 363 60, 323312-317
• CPC Class Codes: H02M 1/0043 Converters switched with a phase shift, i.e. interleaved non-isolated DC/DC converters H02M3/1586
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/072 adapted to generate an output voltage whose value is lower than the input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A system for reducing power loss in a switched-capacitor converter includes a first and second switched capacitor sub-converter each having a flying capacitor and a first, second, third, and fourth switching device. Each switching device is controlled by one of a first, second, third, and fourth clock signal. The first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 1800 degrees out of phase from the first phase. The system also includes a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

Claims

1. A system for reducing power loss in a switched-capacitor converter, the system comprising:

a first and second switched capacitor sub-converter each having

a first, second, third, and fourth switching device each controlled by one of a first, second, third, and fourth clock signal, and

a flying capacitor,

wherein the first, second, third and fourth clock signals of the second switched capacitor sub-converter are inverted such that the first switched capacitor sub-converter operates during a first phase and the second switched capacitor converter operates during a second phase that is 180 degrees out of phase from the first phase; and

,

a resonant charge sharing portion for coupling a bottom-plate parasitic capacitance of the first switched capacitor sub-converter to a bottom-plate parasitic capacitance of the second switched capacitor converter.

2. The system of claim 1, the resonant charge sharing portion comprising a sharing inductor coupled in series with a sharing switch.

3. The system of claim 2, wherein

a capacitance value of the bottom-plate parasitic capacitance is the same for each of the first and second switched capacitor sub-converters, and

the sharing switch is in an on mode for a length of time defined by π

√

{square root over (L_sC_bp/2)}

where L_s is an inductance of the sharing inductor and C_bp is the bottom-plate parasitic capacitance of at least one of the first and second switched capacitor sub-converters.

4. The system of claim 2, wherein

a capacitance value of the bottom-plate parasitic capacitance is not equal for each of the first and second switched capacitors, and

the sharing switch is in an on mode for a length of time is defined by

5. The system of claim 1, the first and second switched capacitor converters being resonant such that a resonant inductor is coupled in series with the flying capacitor.

6. The system of claim 1, wherein, within each first and second switched capacitor converters, the first switching device is electrically coupled between an input node and a first flying node, the second switching device is electrically coupled between the first flying node and an output node, the third switching device is electrically coupled between the output node and a second flying node, and the fourth switching device is electrically coupled between the second flying node and ground.

7. The system of claim 6, wherein, within each of the first and second switched capacitor converters, the flying capacitor is electrically coupled between each of the first and second flying nodes, and a bottom-plate parasitic capacitance is between the second flying node and ground.

8. The system of claim 7, wherein, within each of the first and second switched capacitor converters, a resonant inductor is coupled in series with the flying capacitor between first flying node and the flying capacitor.

9. The system of claim 7, wherein, within each of the first and second switched capacitor converters, a resonant inductor is coupled between the second flying node and the flying capacitor.

10. The system of claim 9, wherein the resonant charge sharing portion comprises a sharing switch, controlled via a fifth clock signal, coupled to the second flying node, within each of the first and second switched capacitor converters.

11. The system of claim 10, wherein the sharing switch is in an on state, as determined by the fifth clock signal, for a length of time defined by