Increasing manufacturing yield of integrated circuits by modifying original design layout using location specific constraints

• US 9,798,853 B2
• Filed: 08/30/2016
• Issued: 10/24/2017
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: IYM Technologies LLC (General Patent Corporation)
• Original Assignee: IYM Technologies LLC (General Patent Corporation)
• Inventors: Qian, Qi-De
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/251,961
• Publication Number:
  US 20160371424A1
• Time in Patent Office: 420 Days
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

Claims

1. An integrated circuit (IC) product manufactured using an IC fabrication system by a process comprising steps of:

providing an original design layout;

providing original global limits on relative distance between layout objects;

detecting a plurality of areas in the original design layout that include patterns that increase manufacturing defect risk;

generating location specific modifications to the original global limits, the location specific modifications comprising a first location specific limit on relative distance between layout objects for a first area in the plurality of areas in the original design layout, wherein the first location specific limit reduces manufacturing defect risk for the first area;

modifying the original design layout by enforcing the original global limits with the location specific modifications to generate a modified design layout, the modified design layout being different from the original design layout, so that the original global limits and the location specific modifications work together to improve chip yield;

providing the modified design layout to the IC fabrication system;

wherein a chip yield exhibited by manufacturing the integrated circuit product by the IC fabrication system using the modified design layout is higher than a chip yield that would be exhibited by the IC fabrication system using the original design layout; and

the steps of detecting, generating, and modifying are performed by a processing system comprising a memory device storing application software, a user interface, and a processor coupled to the memory device and to the user interface.

2. The integrated circuit product of claim 1, wherein a dimension of a plurality of first directionally oriented layout objects of a first type of the modified design layout is substantially different from same dimension of a plurality of second directionally oriented layout objects of the first type, the first directionally oriented layout objects being oriented along a first direction, the second directionally oriented layout objects being oriented along a second direction, the second direction being orthogonal to the first direction.

3. The integrated circuit product of claim 2, wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects reside in the same layer of the modified design layout.

4. The integrated circuit product of claim 3, wherein the plurality of the first directionally oriented layout objects and the plurality of second directionally oriented objects are conductors.

5. The integrated circuit product of claim 1, wherein the integrated circuit product comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values.

6. The integrated circuit product of claim 5, wherein the first plurality of routing wires and the second plurality of routing wires reside in the same layer of the modified design layout.

7. The integrated circuit product of claim 1, wherein the original design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances.

8. The integrated circuit product of claim 1, wherein the first area includes interrelated layout objects on one layer.

9. The integrated circuit product of claim 8, wherein the step of generating the location specific modifications comprises comparing known geometry combinations.

10. The integrated circuit product of claim 9, wherein the step of generating the location specific modifications comprises using a look-up data table to obtain the location specific modifications using known geometry combinations as a pattern key to search the look-up table.

11. The integrated circuit product of claim 8, wherein the step of generating the location specific modifications comprises performing pattern recognition.

12. The integrated circuit product of claim 8, wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one interrelated layout object.

13. The integrated circuit product of claim 8, wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent interrelated layout objects.

14. The integrated circuit product of claim 13, wherein the at least two adjacent interrelated layout objects are conductors.

15. The integrated circuit product of claim 1, wherein the step of generating the location specific modifications comprises comparing known geometry combinations.

16. The integrated circuit product of claim 1, wherein the step of generating the location specific modifications comprises using a look-up data table to obtain the location specific modifications using known geometry combinations as a pattern key to search the look-up table.

17. The integrated circuit product of claim 1, wherein the step of generating the location specific modifications comprises performing pattern recognition.

18. The integrated circuit product of claim 1, wherein the step of modifying the original design layout comprises adjusting at least a width value of at least one layout object.

19. The integrated circuit product of claim 1, wherein the step of modifying the original design layout comprises adjusting spacing between at least two adjacent layout objects.

20. The integrated circuit product of claim 1, wherein:

the original global limits comprise a first minimum safeguard distance limit and

the step of generating the location specific modifications comprises generating a first additional safeguard distance, and adding the first additional safeguard distance to the first minimum safeguard distance limit to obtain the first location specific limit.

21. The integrated circuit product of claim 1, wherein application of the original global limits together with the first location specific limit in the first area is more restrictive than application of the original global limits without application of the first location specific limit in the first area, whereby the modified design layout satisfies the original global limits.

22. The integrated circuit product of claim 1, wherein the process further comprises step of applying the original global limits to the original design layout.