Resistance change memory

• US 9,799,385 B2
• Filed: 03/10/2015
• Issued: 10/24/2017
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Fujita, Katsuyuki
• Primary Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US14/644,148
• Publication Number:
  US 20160071567A1
• Time in Patent Office: 959 Days
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor.

Claims

1. A resistance change memory comprising:

a memory cell comprising a resistance change element;

a reference voltage generating circuit which generates a reference adjustment voltage;

a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and

a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor,

wherein the reference voltage generating circuit comprises a negative feedback circuit, the negative feedback circuit including a second transistor having a gate coupled to a gate of the first transistor, and an operational amplifier which sets a drain of the second transistor to a predetermined voltage.

2. The resistance change memory according to claim 1, wherein:

the drain of the second transistor is coupled to a noninverting input terminal of the operational amplifier,

the gate of the second transistor is coupled to an output terminal of the operational amplifier, and

an inverting input terminal of the operational amplifier is coupled to a resistance dividing circuit which produces the predetermined voltage.

3. The resistance change memory according to claim 1, wherein the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in resistance value in response to a change of the reference adjustment voltage.

4. The resistance change memory according to claim 1, further comprising a first circuit which generates a first current,

wherein the reference voltage generating circuit supplies a second current corresponding to the first current to the drain of the second transistor.

5. The resistance change memory according to claim 4, wherein the first circuit comprises a second circuit which increases the first current as the temperature rises, and a third circuit which decreases the first current as the temperature rises.

6. The resistance change memory according to claim 5, wherein the second circuit includes a diode, and the third circuit includes a resistor.

7. The resistance change memory according to claim 4, wherein:

the first circuit comprises a second circuit which comprises a magnetic tunnel junction (MTJ) element having parallel magnetization, and a third circuit which comprises an MTJ element having antiparallel magnetization, and

the first current is generated from a current flowing through the second circuit and a current flowing through the third circuit.

8. The resistance change memory according to claim 1, wherein:

the drain of the second transistor is coupled to a noninverting input terminal of the operational amplifier,

the gate of the second transistor is coupled to an output terminal of the operational amplifier,

an inverting input terminal of the operational amplifier is coupled to a first circuit which produces the predetermined voltage, and

the first circuit changes the predetermined voltage in accordance with a temperature of the first circuit.

9. The resistance change memory according to claim 1, further comprising a memory cell array comprising memory cells including the memory cell.

10. The resistance change memory according to claim 1, wherein the resistance change element comprises a magnetic tunnel junction (MTJ) element.

11. The resistance change memory according to claim 1 comprising at least one of a magnetoresistive random access memory (MRAM), a resistive random access memory (ReRAM) and a phase-change random access memory (PCRAM).

12. The resistance change memory according to claim 1, wherein the source is directly grounded during a read operation.

13. A resistance change memory comprising:

a memory cell comprising a resistance change element;

a reference voltage generating circuit which generates a reference adjustment voltage;

a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and

a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor,

wherein;

the reference adjustment voltage changes in accordance with a temperature of the reference voltage generating circuit,

the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in resistance value in response to a change of the reference adjustment voltage, and

the reference adjustment voltage is not applied to a circuit that is electrically connected between the memory cell and the sense amplifier.

14. The resistance change memory according to claim 13, wherein the reference voltage generating circuit increases the reference adjustment voltage as the temperature rises.

15. The resistance change memory according to claim 13, wherein the reference voltage generating circuit decreases the reference adjustment voltage as the temperature rises.

16. The resistance change memory according to claim 13, wherein the source is directly grounded during a read operation.