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Memory device comprising electrically floating body transistor

  • US 9,799,392 B2
  • Filed: 10/07/2016
  • Issued: 10/24/2017
  • Est. Priority Date: 08/15/2014
  • Status: Active Grant
First Claim
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1. A method of operating a semiconductor memory cell comprising:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell;

    a first region in electrical contact with said floating body region, located at a surface of said floating body region;

    a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;

    a gate positioned between said first region and said second region; and

    a third region in electrical contact with said floating body region, located below said floating body region;

    said method comprising;

    applying a first set of bias conditions to said memory cell;

    measuring a first current;

    applying a second set of bias conditions to said memory cell;

    measuring a second current; and

    comparing said first current and said current to determine said state of the memory cell.

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