Memory device comprising electrically floating body transistor

• US 9,799,392 B2
• Filed: 10/07/2016
• Issued: 10/24/2017
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Berger, Neal, Widjaja, Yuniarto
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/287,903
• Publication Number:
  US 20170025164A1
• Time in Patent Office: 382 Days
• Field of Search: 36518907, 36521012
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Claims

1. A method of operating a semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region, located at a surface of said floating body region;

a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;

a gate positioned between said first region and said second region; and

a third region in electrical contact with said floating body region, located below said floating body region;

said method comprising;

applying a first set of bias conditions to said memory cell;

measuring a first current;

applying a second set of bias conditions to said memory cell;

measuring a second current; and

comparing said first current and said current to determine said state of the memory cell.

2. The method of operating a semiconductor memory cell of claim 1, further comprising applying a bias to said third region to maintain said state of the memory cell.

3. The method of operating a semiconductor memory cell of claim 2, wherein said bias to said third region is a constant positive voltage.

4. The method of operating a semiconductor memory cell of claim 2, wherein said bias to said third region is a periodic pulse of positive voltage.

5. The method of operating a semiconductor memory cell of claim 1, wherein said first current and said second current flow from said first region to said second region.

6. The method of operating a semiconductor memory cell of claim 5, wherein a difference between a magnitude of said first current and a magnitude of said second current is greater when said memory cell is in the first state than when said memory cell is in the second state.

7. The method of operating a semiconductor memory cell of claim 6, wherein a charge level of said floating body in said first state is more positive than a charge level of said floating body in said second state.

8. The method of operating a semiconductor memory cell of claim 1, wherein said applying a first set of bias conditions comprises applying a first bias condition to said third region, and applying a second set of bias conditions comprises applying a second bias condition to said third region.

9. The method of operating a semiconductor memory cell of claim 1, wherein said applying a first set of bias conditions comprises applying said first set of bias conditions to said first region, said second region, and said gate, and said applying a second set of bias conditions comprises applying said second set of bias conditions to said first region, said second region, and said gate.

10. The method of operating a semiconductor memory cell of claim 1, further comprising applying a third set of bias conditions to said memory cell and applying a fourth set of bias conditions to said memory cell.