Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction

• US 9,799,405 B1
• Filed: 07/29/2015
• Issued: 10/24/2017
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: Polaris PowerLED Technologies, LLC (Microchip Technology Incorporated)
• Original Assignee: Ip Gem Group, LLC
• Inventors: Micheloni, Rino, Marelli, Alessia, Bates, Stephen
• Primary Examiner(s): Lamarre, Guy
• Application Number:
  US14/812,891
• Time in Patent Office: 818 Days
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.

Claims

1. A method for reducing latency of a nonvolatile memory controller comprising:

storing at least one table indicating threshold voltage shift read instructions, threshold voltage offset values and corresponding index values for a nonvolatile memory device;

determining at the nonvolatile memory controller a first usage characteristic of the nonvolatile memory device;

determining, at a nonvolatile memory controller, whether the first usage characteristic is greater than or equal to a usage characteristic threshold; and

when the first usage characteristic is determined to be greater than or equal to the usage characteristic threshold, performing all subsequent reads of the nonvolatile memory device by;

indexing the at least one table using an index that corresponds to a second usage characteristic of the nonvolatile memory device to identify the corresponding threshold voltage shift read instruction and the corresponding threshold voltage offset value; and

sending the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

2. The method of claim 1 wherein the indexing further comprises indexing the at least one table using an index that corresponds to the second usage characteristic to identify a corresponding enhanced threshold voltage shift read instruction, or the corresponding threshold voltage shift read instruction and the corresponding threshold voltage offset value, and wherein the sending further includes sending the identified enhanced threshold voltage shift read instruction or the identified threshold voltage shift read instruction and threshold voltage offset value to the nonvolatile memory device.

3. The method of claim 1 wherein the first usage characteristic is a number of program and erase cycles of the nonvolatile memory device and wherein the usage characteristic threshold comprises a threshold number of program and erase cycles.

4. The method of claim 1 wherein the usage characteristic threshold is an error threshold, the method further comprising:

each time that a read of a codeword of a nonvolatile memory device is performed by the nonvolatile memory controller, determining the number of errors in the codeword; and

wherein the determining, at a nonvolatile memory controller, whether the first usage characteristic is greater than or equal to a usage characteristic threshold further comprises determining whether the number of errors in the codeword is greater than or equal to the error threshold.

5. The method of claim 1 wherein the second usage characteristic is a number of program and erase cycles of the nonvolatile memory device.

6. The method of claim 1 wherein the first usage characteristic is the number of program and erase cycles of the nonvolatile memory device, the method further comprising:

determining a retention characteristic of the nonvolatile memory device; and

wherein the indexing further comprises indexing the at least one table using an index that corresponds to the determined number of program and erase cycles of the nonvolatile memory device and the determined retention characteristic of the nonvolatile memory device.

7. A method for reducing latency of a nonvolatile memory controller comprising:

storing at least one table indicating threshold voltage shift read instructions, threshold voltage offset values and corresponding index values; and

performing all reads of a nonvolatile memory device that is coupled to the nonvolatile memory controller by;

determining, at the nonvolatile memory controller, a usage characteristic of the nonvolatile memory device;

indexing the at least one table using an index that corresponds to the determined usage characteristic to identify a corresponding threshold voltage shift read instruction and a corresponding threshold voltage offset value; and

sending the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

8. The method of claim 7 wherein the indexing further comprises indexing the at least one table using an index that corresponds to the determined usage characteristic to identify an enhanced threshold voltage shift read instruction or the corresponding threshold voltage shift read instruction and the corresponding threshold voltage offset value, and wherein the sending further comprises sending the identified enhanced threshold voltage shift read instruction or the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

9. The method of claim 7 wherein the nonvolatile memory controller is an integrated circuit device and the nonvolatile memory device is a different integrated circuit device.

10. The method of claim 7 wherein the usage characteristic is the number of program and erase cycles of the nonvolatile memory device.

11. The method of claim 10 further comprising:

determining a retention characteristic of the nonvolatile memory device; and

wherein the indexing further comprises indexing the at least one table using an index that corresponds to the determined number of program and erase cycles and the determined retention characteristic of the nonvolatile memory device.

12. A nonvolatile memory controller comprising;

a storage module configured to store threshold voltage shift read instructions, threshold voltage offset values and corresponding index values, each of the threshold voltage shift read instructions and the threshold voltage offset values associated with one or more of the index values;

a status circuit configured to determine a first usage characteristic of a nonvolatile memory device; and

a read circuit configured to determine whether the first usage characteristic is greater than or equal to a usage characteristic threshold and when the first usage characteristic is greater than or equal to the usage characteristic threshold, the read circuit configured to perform all subsequent reads of the nonvolatile memory device by identifying the stored threshold voltage shift read instruction associated with one or more index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value associated with one or more index value that corresponds to the second usage characteristic, and sending the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

13. The nonvolatile memory controller of claim 12 wherein the identifying further comprises identifying an enhanced threshold voltage shift read instruction, or the stored threshold voltage shift read instruction and the stored threshold voltage offset value associated with one or more index value that corresponds to the second usage characteristic, and wherein the sending further comprises sending the identified enhanced threshold voltage shift read instruction, or the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

14. The nonvolatile memory controller of claim 12 wherein the first usage characteristic and the second usage characteristic are a number of program and erase cycles.

15. The nonvolatile memory controller of claim 12 wherein the nonvolatile memory controller is an integrated circuit device and the nonvolatile memory device is a different integrated circuit device.

16. The nonvolatile memory controller of claim 12 wherein the storage module is configured to store at least one table indicating the threshold voltage shift read instructions, the threshold voltage offset values and the corresponding index values, the nonvolatile memory controller further comprising:

an online test circuit configured to periodically perform an online retention test, the online retention test including reading codewords in test blocks of nonvolatile memory devices electrically coupled to the nonvolatile memory controller, the status circuit configured to determine the number of program and erase cycles after each program and erase cycle of the nonvolatile memory device; and

wherein, the identifying the stored threshold voltage shift read instruction associated with one or more index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value corresponding to one or more index value that corresponds to the second usage characteristic further includes indexing the at least one table to identify the threshold voltage shift read instruction and the stored threshold voltage offset value associated with one or more index value corresponding to the most recently determined number of program and erase cycles for the nonvolatile memory device and the results from the most recent online retention test.

17. The nonvolatile memory controller of claim 16 further comprising:

an offline test circuit configured to perform an offline retention test by reading codewords of at least one test block at a first time to determine the number of errors in each codeword, determining the number of errors in the codeword having the highest number of errors at the first time, after power off of the memory controller and after powering-on the memory controller at a subsequent time reading the codewords of the at least one test block, determining the number of errors in the codeword having the highest number of errors at the subsequent time, calculating a delta worst value by subtracting the number of errors in the codeword having the highest number of errors at the first time from the number of errors in the codeword having the highest number of errors at the subsequent time; and

wherein the identifying the stored threshold voltage shift read instruction associated with the index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value associated with the index value that corresponds to the second usage characteristic further includes indexing the at least one table to identify the threshold voltage shift read instruction and the threshold voltage offset value associated with one or more index value corresponding to the most recently determined number of program and erase cycles for the nonvolatile memory device and the delta worst value from the most recent offline retention test.

18. A nonvolatile memory controller comprising:

a storage module configured to store threshold voltage shift read instructions, threshold voltage offset values and corresponding index values, each of the threshold voltage shift read instructions and the threshold voltage offset values associated with one or more of the index values;

a status circuit configured to determine a usage characteristic of a nonvolatile memory device; and

a read circuit configured to perform all reads of the nonvolatile memory device by identifying the stored threshold voltage shift read instruction associated with one or more index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value associated with one or more index value that corresponds to the second usage characteristic, and sending the identified threshold voltage shift read instruction and the identified threshold voltage offset value to the nonvolatile memory device.

19. The nonvolatile memory controller of claim 18 wherein the stored data comprises a table that includes threshold voltage shift read instructions, threshold voltage offset values and corresponding index values, the nonvolatile memory controller further including:

an online test circuit configured to periodically perform an online retention test, the online retention test including reading codewords in test blocks of the nonvolatile memory device, the status circuit configured to determine the number of program and erase cycles after each program and erase cycle of the nonvolatile memory device and wherein the usage characteristic is the determined number of program and erase cycles; and

wherein the identifying the stored threshold voltage shift read instruction associated with one or more index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value associated with one or more index value that corresponds to the second usage characteristic further includes identifying the stored threshold voltage shift read instruction and the stored threshold voltage offset value associated with one or more index value corresponding to the most recently determined number of program and erase cycles for the nonvolatile memory device and the results from the most recent online retention test.

20. The nonvolatile memory controller of claim 19 further comprising:

an offline test circuit configured to perform an offline retention test by reading codewords of at least one test block at a first time to determine the number of errors in each codeword, determining the number of errors in the codeword having the highest number of errors at the first time, after power off of the memory controller and after powering-on the memory controller at a subsequent time reading the codewords of the at least one test block, determining the number of errors in the codeword having the highest number of errors at the subsequent time, calculating a delta worst value by subtracting the number of errors in the codeword having the highest number of errors at the first time from the number of errors in the codeword having the highest number of errors at the subsequent time; and

wherein the identifying the stored threshold voltage shift read instruction associated with one or more index value that corresponds to a second usage characteristic and identifying the stored threshold voltage offset value associated with one or more index value that corresponds to the second usage characteristic further comprises identifying the stored threshold voltage shift read instruction and the stored threshold voltage offset value associated with one or more index value corresponding to the most recently determined number of program and erase cycles for the nonvolatile memory device and the delta worst value from the most recent offline retention test.