Integrated circuit containing DOEs of NCEM-enabled fill cells

• US 9,799,575 B2
• Filed: 04/04/2016
• Issued: 10/24/2017
• Est. Priority Date: 12/16/2015
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Belousov, Alexander
• Application Number:
  US15/090,256
• Publication Number:
  US 20170178981A1
• Time in Patent Office: 568 Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11885 Two levels of metal
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/45 : Ohmic electrodes

Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Claims

1. An integrated circuit (IC), comprising at least:

a standard cell area that includes a mix of at least one thousand logic cells and fill cells of different widths and uniform heights, placed into at least twenty adjacent rows, with at least twenty cells placed side-by-side in each row;

wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising a plurality of similarly-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;

a NCEM pad, formed in a conductive layer, said NCEM pad being at least two times larger, in at least one dimension, than a minimum size permitted by design rules;

a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;

a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad; and

,

a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;

wherein each of the similarly-configured, NCEM-enabled fill cells in the first DOE is configured to render a first selected manufacturing failure observable as an abnormal pad-to-ground leakage, conductance, or resistance, detected by voltage contrast (VC) inspection of the NCEM pad; and

,

wherein the similarly-configured, NCEM-enabled fill cells of the first DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormal pad-to-ground leakage, conductance, or resistance as a result of said first selected manufacturing failure.

2. An IC, as defined in claim 1, further comprising at least:

a second DOE, comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;

a NCEM pad, formed in a conductive layer, said pad being at least two times larger, in at least one dimension, than the minimum size permitted by design rules;

a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;

a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad; and

,

a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;

wherein each of the similarly-configured, NCEM-enabled fill cells in the second DOE is configured to render a second selected manufacturing failure observable as an abnormal pad-to-ground leakage, conductance, or resistance, detected by VC inspection of the NCEM pad, and wherein the second selected manufacturing failure is different than the first selected manufacturing failure; and

,

wherein the similarly-configured, NCEM-enabled fill cells of the second DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormal pad-to-ground leakage, conductance, or resistance as a result of said second selected manufacturing failure.

3. An IC, as defined in claim 2, wherein the first selected manufacturing failure involves short or leakage defects that present as abnormally high pad-to-ground conductance or leakage, and the second selected manufacturing failure involves open or resistance defects that present as abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance.

4. An IC, as defined in claim 3, wherein both the first and second selected manufacturing failures involve layers in a connector stack region of the IC.

5. An IC, as defined in claim 2, further comprising at least:

a third DOE, comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;

a NCEM pad, formed in a conductive layer, said NCEM pad being at least two times larger, in at least one dimension, than the minimum size permitted by design rules;

a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;

a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad; and

,

a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;

wherein each of the similarly-configured NCEM-enabled fill cells in the third DOE is configured to render a third selected manufacturing failure observable as an abnormal pad-to-ground leakage, conductance or resistance, detected by VC inspection of the NCEM pad, and wherein the third selected manufacturing failure is different than the first selected manufacturing failure, and is different than the second selected manufacturing failure; and

,

wherein the similarly-configured NCEM-enabled fill cells of the third DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormal pad-to-ground leakage, conductance or resistance as a result of said third selected manufacturing failure.

6. An IC, as defined in claim 5, wherein each of said first, second, and third DOEs include NCEM-enabled fill cells in at least three variants.

7. An IC, as defined in claim 6, wherein each of said first, second, and third DOEs include NCEM-enabled fill cells in at least five variants.

8. An IC, as defined in claim 5, wherein the NCEM-enabled fill cells of the first, second, and third DOEs are irregularly distributed within the standard cell area of the IC.

9. An IC, as defined in claim 1, wherein each variant differs from the other(s) only in the position, size, or shape of its first or second mask-patterned feature.

10. An IC, as defined in claim 1, wherein the variants differs only by a single dimensional parameter that characterizes their respective test areas.

11. An integrated circuit (IC), comprising at least:

a standard cell area that includes a mix of at least one thousand logic cells and fill cells of different widths and uniform heights, placed into at least twenty adjacent rows, with at least twenty cells placed side-by-side in each row;

wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;

a NCEM pad, formed in one or more conductive layer(s), said NCEM pad being at least two times larger, in at least one dimension, than the minimum size permitted by design rules;

a rectangular test area defined by selected boundaries of a plurality of mask-patterned features, said test area characterized by two dimensional parameters, said plurality of mask-patterned features including at least first and second features that are electrically connected in the absence of a first manufacturing failure;

a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad; and

,

a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;

wherein each of the similarly-configured NCEM-enabled fill cells in the first DOE is configured to render a first selected manufacturing failure observable as an abnormally high pad-to-ground conductance or leakage, detected by VC inspection of the NCEM pad;

wherein the similarly-configured NCEM-enabled fill cells of the first DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormally high pad-to-ground conductance or leakage as a result of said first selected manufacturing failure; and

,

wherein the similarly-configured NCEM-enabled fill cells of the first DOE are selected from the list consisting of;

source/drain (AA)-tip-to-tip-short-configured, NCEM-enabled fill cells;

source/drain contact (AACNT)-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

source/drain silicide (TS)-tip-to-tip-short-configured, NCEM-enabled fill cells;

gate (GATE)-tip-to-tip-short-configured, NCEM-enabled fill cells;

gate contact (GATECNT)-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

first wiring layer (M1)-tip-to-tip-short-configured, NCEM-enabled fill cells;

via to interconnect stack (V0)-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

first interconnect via (V1)-M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second wiring layer (M2)-tip-to-tip-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second interconnect via (V2)-M2-tip-to-tip-short-configured, NCEM-enabled fill cells;

third wiring layer (M3)-tip-to-tip-short-configured, NCEM-enabled fill cells;

V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

AA-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V0-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-side-short-configured, NCEM-enabled fill cells;

AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

M1-side-to-side-short-configured, NCEM-enabled fill cells;

V0-side-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-side-to-side-short-configured, NCEM-enabled fill cells;

V1-side-to-side-short-configured, NCEM-enabled fill cells;

M2-side-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-side-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-side-to-side-short-configured, NCEM-enabled fill cells;

V2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-side-to-side-short-configured, NCEM-enabled fill cells;

AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-V2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AA-diagonal-short-configured, NCEM-enabled fill cells;

TS-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-AA-diagonal-short-configured, NCEM-enabled fill cells;

GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

M1-diagonal-short-configured, NCEM-enabled fill cells;

V0-diagonal-short-configured, NCEM-enabled fill cells;

M1-V0-diagonal-short-configured, NCEM-enabled fill cells;

V1-M1-diagonal-short-configured, NCEM-enabled fill cells;

V1-diagonal-short-configured, NCEM-enabled fill cells;

M2-diagonal-short-configured, NCEM-enabled fill cells;

M2-V1-diagonal-short-configured, NCEM-enabled fill cells;

M3-diagonal-short-configured, NCEM-enabled fill cells;

V2-M2-diagonal-short-configured, NCEM-enabled fill cells;

V2-diagonal-short-configured, NCEM-enabled fill cells;

M3-V2-diagonal-short-configured, NCEM-enabled fill cells;

AA-corner-short-configured, NCEM-enabled fill cells;

AACNT-corner-short-configured, NCEM-enabled fill cells;

AACNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-TS-corner-short-configured, NCEM-enabled fill cells;

GATECNT-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cells;

M1-corner-short-configured, NCEM-enabled fill cells;

V0-corner-short-configured, NCEM-enabled fill cells;

M1-V0-corner-short-configured, NCEM-enabled fill cells;

V1-M1-corner-short-configured, NCEM-enabled fill cells;

V1-corner-short-configured, NCEM-enabled fill cells;

M2-corner-short-configured, NCEM-enabled fill cells;

M2-V1-corner-short-configured, NCEM-enabled fill cells;

M3-corner-short-configured, NCEM-enabled fill cells;

V2-M2-corner-short-configured, NCEM-enabled fill cells;

V2-corner-short-configured, NCEM-enabled fill cells;

M3-V2-corner-short-configured, NCEM-enabled fill cells;

GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V1-V0-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M2-M1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V2-V1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M3-M2-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-AACNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V1-M1-via-chamfer-short-configured, NCEM-enabled fill cells;

V2-M2-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-merged-via-short-configured, NCEM-enabled fill cells;

V1-merged-via-short-configured, NCEM-enabled fill cells; and

,

V2-merged-via-short-configured, NCEM-enabled fill cells;

a second DOE, comprising a plurality of similarly-configured, NCEM-enabled fill cells, wherein each NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in a connector or interconnect stack layer, extending across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of said standard cell region;

a NCEM pad, formed in a conductive layer, said NCEM pad being at least two times larger, in at least one dimension, than a minimum size permitted by design rules;

a rectangular test area defined by selected boundaries of at least first and second distinct, mask-patterned features, said test area being characterized by two dimensional parameters;

a first conductive pathway that electrically connects the first mask-patterned feature to said NCEM pad; and

,

a second conductive pathway that electrically connects the second mask-patterned feature to a permanently or virtually grounded structure;

wherein each of the similarly-configured, NCEM-enabled fill cells in the second DOE is configured to render a second selected manufacturing failure observable as an abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detected by VC inspection of the NCEM pad; and

,

wherein the similarly-configured, NCEM-enabled fill cells of the second DOE include a plurality of variants, where the variants differ in terms of their respective probability of presenting an abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance as a result of said second selected manufacturing failure; and

,

wherein the similarly-configured NCEM-enabled fill cells of the second DOE are selected from the list consisting of;

AA-snake-open-configured, NCEM-enabled fill cells;

TS-snake-open-configured, NCEM-enabled fill cells;

AACNT-snake-open-configured, NCEM-enabled fill cells;

GATE-snake-open-configured, NCEM-enabled fill cells;

GATECNT-snake-open-configured, NCEM-enabled fill cells;

V0-snake-open-configured, NCEM-enabled fill cells;

M1-snake-open-configured, NCEM-enabled fill cells;

V1-snake-open-configured, NCEM-enabled fill cells;

M2-snake-open-configured, NCEM-enabled fill cells;

V2-snake-open-configured, NCEM-enabled fill cells;

M3-snake-open-configured, NCEM-enabled fill cells;

AA-stitch-open-configured, NCEM-enabled fill cells;

TS-stitch-open-configured, NCEM-enabled fill cells;

AACNT-stitch-open-configured, NCEM-enabled fill cells;

GATECNT-stitch-open-configured, NCEM-enabled fill cells;

V0-stitch-open-configured, NCEM-enabled fill cells;

M1-stitch-open-configured, NCEM-enabled fill cells;

V1-stitch-open-configured, NCEM-enabled fill cells;

M2-stitch-open-configured, NCEM-enabled fill cells;

V2-stitch-open-configured, NCEM-enabled fill cells;

M3-stitch-open-configured, NCEM-enabled fill cells;

AACNT-TS-via-open-configured, NCEM-enabled fill cells;

AACNT-AA-via-open-configured, NCEM-enabled fill cells;

TS-AA-via-open-configured, NCEM-enabled fill cells;

GATECNT-GATE-via-open, NCEM-enabled fill cells;

V0-GATECNT-via-open-configured, NCEM-enabled fill cells;

V0-AA-via-open-configured, NCEM-enabled fill cells;

V0-TS-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-via-open-configured, NCEM-enabled fill cells;

V0-GATE-via-open-configured, NCEM-enabled fill cells;

V0-via-open-configured, NCEM-enabled fill cells;

M1-V0-via-open-configured, NCEM-enabled fill cells;

V1-M1-via-open-configured, NCEM-enabled fill cells;

V1-M2-via-open-configured, NCEM-enabled fill cells;

M1-GATECNT-via-open-configured, NCEM-enabled fill cells;

M1-AANCT-via-open-configured, NCEM-enabled fill cells;

V2-M2-via-open-configured, NCEM-enabled fill cells;

V2-M3-via-open-configured, NCEM-enabled fill cells;

M1-metal-island-open-configured, NCEM-enabled fill cells;

M2-metal-island-open-configured, NCEM-enabled fill cells;

M3-metal-island-open-configured, NCEM-enabled fill cells;

V0-merged-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-merged-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-merged-via-open-configured, NCEM-enabled fill cells;

V1-merged-via-open-configured, NCEM-enabled fill cells;

V2-merged-via-open-configured, NCEM-enabled fill cells;

V1-M1-merged-via-open-configured, NCEM-enabled fill cells; and

,

V2-M2-merged-via-open-configured, NCEM-enabled fill cells.